[llvm] [ARM][TableGen][MC] Change the ARM mnemonic operands to be optional for ASM parsing (PR #83436)

[via llvm-commits]

dyung wrote:

> Hi @dyung, Looking at the architecture reference manual (https://developer.arm.com/documentation/ddi0597/2023-09/?lang=en) I dont recognise these encodings.
> 
> Perhaps we previously parsed these but shouldn't have? (For me it causes a crash on old builds?).
> 
> In this case they would both need an extra operands. eg.
> 
> ```
>         strexd  r0, r2, r3, [r3]                @ encoding: [0x90,0x0f,0xa3,0xe1]
>         ldrexd  r0, r1, [r2]                    @ encoding: [0x9f,0x0f,0xb2,0xe1]
> ```
> 
> (I'm guessing at the missing registers)
> 
> Is the source for the project which these came from public?

The code is unfortunately not from a public codebase.

I am told that it is a short form of essentially the longer form you posted. If you try earlier versions of clang and compile directly to an object file and disassemble it, I believe it generated the assembly you mentioned. (I also noticed that earlier versions of clang hit an assertion failure when generating the assembly)

https://github.com/llvm/llvm-project/pull/83436