[lld] [LLD][RISCV] Add relaxation for absolute int12 Hi20Lo12 (PR #86124)

[Philip Reames via llvm-commits]

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@@ -464,6 +467,20 @@ void RISCV::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const {
     return;
   }
 
+  case INTERNAL_R_RISCV_X0REL_I:
+  case INTERNAL_R_RISCV_X0REL_S: {
+    assert(isInt<12>(val));
+    uint64_t hi = (val + 0x800) >> 12;
+    uint64_t lo = val - (hi << 12);
+    uint32_t insn = (read32le(loc) & ~(31 << 15)) | (X_X0 << 15);
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preames wrote:

To call out one possible concern with this patch.  If there is an IType or SType instruction whose encoding reserved rs1=x0 (or otherwise gave it distinct behavior) this transform would not be legal.  I did a search through the ISA manual and didn't find anything, but that doesn't mean such a special case definitely doesn't exist.  In principal such a special case is also possible for GP, but there's a lot more precedent for X0 being special in the encoding (though usually as the value for RD).  

https://github.com/llvm/llvm-project/pull/86124