[llvm] 686f459 - [ARM] Regenerate some check lines. NFC
David Green via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 21 06:45:49 PDT 2024
Author: David Green
Date: 2024-03-21T13:45:44Z
New Revision: 686f4599cfa444aa62db4e22bf752f3d9614c30d
URL: https://github.com/llvm/llvm-project/commit/686f4599cfa444aa62db4e22bf752f3d9614c30d
DIFF: https://github.com/llvm/llvm-project/commit/686f4599cfa444aa62db4e22bf752f3d9614c30d.diff
LOG: [ARM] Regenerate some check lines. NFC
Added:
Modified:
llvm/test/CodeGen/ARM/arm-and-tst-peephole.ll
llvm/test/CodeGen/ARM/select.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/ARM/arm-and-tst-peephole.ll b/llvm/test/CodeGen/ARM/arm-and-tst-peephole.ll
index 365727c9dd27d5..0795525fba1b3a 100644
--- a/llvm/test/CodeGen/ARM/arm-and-tst-peephole.ll
+++ b/llvm/test/CodeGen/ARM/arm-and-tst-peephole.ll
@@ -8,10 +8,8 @@
%struct.Foo = type { ptr }
-; ARM-LABEL: foo:
-; THUMB-LABEL: foo:
-; T2-LABEL: foo:
define ptr @foo(ptr %this, i32 %acc) nounwind readonly align 2 {
+; ARM-LABEL: foo:
; ARM: @ %bb.0: @ %entry
; ARM-NEXT: add r2, r0, #4
; ARM-NEXT: mov r12, #1
@@ -44,6 +42,7 @@ define ptr @foo(ptr %this, i32 %acc) nounwind readonly align 2 {
; ARM-NEXT: add r0, r0, r1, lsl #2
; ARM-NEXT: mov pc, lr
;
+; THUMB-LABEL: foo:
; THUMB: @ %bb.0: @ %entry
; THUMB-NEXT: .save {r4, r5, r7, lr}
; THUMB-NEXT: push {r4, r5, r7, lr}
@@ -91,6 +90,7 @@ define ptr @foo(ptr %this, i32 %acc) nounwind readonly align 2 {
; THUMB-NEXT: pop {r0}
; THUMB-NEXT: bx r0
;
+; T2-LABEL: foo:
; T2: @ %bb.0: @ %entry
; T2-NEXT: adds r2, r0, #4
; T2-NEXT: mov.w r12, #1
@@ -125,6 +125,7 @@ define ptr @foo(ptr %this, i32 %acc) nounwind readonly align 2 {
; T2-NEXT: add.w r0, r0, r1, lsl #2
; T2-NEXT: bx lr
;
+; V8-LABEL: foo:
; V8: @ %bb.0: @ %entry
; V8-NEXT: adds r2, r0, #4
; V8-NEXT: mov.w r12, #1
@@ -210,11 +211,8 @@ sw.epilog: ; preds = %tailrecurse.switch
%struct.S = type { ptr, [1 x i8] }
-; ARM-LABEL: bar:
-; THUMB-LABEL: bar:
-; T2-LABEL: bar:
-; V8-LABEL: bar:
define internal zeroext i8 @bar(ptr %x, ptr nocapture %y) nounwind readonly {
+; ARM-LABEL: bar:
; ARM: @ %bb.0: @ %entry
; ARM-NEXT: ldrb r2, [r0, #4]
; ARM-NEXT: ands r2, r2, #112
@@ -230,6 +228,7 @@ define internal zeroext i8 @bar(ptr %x, ptr nocapture %y) nounwind readonly {
; ARM-NEXT: mov r0, #1
; ARM-NEXT: mov pc, lr
;
+; THUMB-LABEL: bar:
; THUMB: @ %bb.0: @ %entry
; THUMB-NEXT: ldrb r2, [r0, #4]
; THUMB-NEXT: movs r3, #112
@@ -253,6 +252,7 @@ define internal zeroext i8 @bar(ptr %x, ptr nocapture %y) nounwind readonly {
; THUMB-NEXT: ands r0, r1
; THUMB-NEXT: bx lr
;
+; T2-LABEL: bar:
; T2: @ %bb.0: @ %entry
; T2-NEXT: ldrb r2, [r0, #4]
; T2-NEXT: ands r2, r2, #112
@@ -270,6 +270,7 @@ define internal zeroext i8 @bar(ptr %x, ptr nocapture %y) nounwind readonly {
; T2-NEXT: movs r0, #1
; T2-NEXT: bx lr
;
+; V8-LABEL: bar:
; V8: @ %bb.0: @ %entry
; V8-NEXT: ldrb r2, [r0, #4]
; V8-NEXT: ands r2, r2, #112
diff --git a/llvm/test/CodeGen/ARM/select.ll b/llvm/test/CodeGen/ARM/select.ll
index 4bb79651f04029..24ca9aeac7f2db 100644
--- a/llvm/test/CodeGen/ARM/select.ll
+++ b/llvm/test/CodeGen/ARM/select.ll
@@ -1,14 +1,25 @@
-; RUN: llc -mtriple=arm-apple-darwin %s -o - | FileCheck %s
-
-; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 %s -o - \
-; RUN: | FileCheck %s --check-prefix=CHECK-VFP
-
-; RUN: llc -mtriple=thumbv7-apple-darwin -mattr=+neon,+thumb2 %s -o - \
-; RUN: | FileCheck %s --check-prefix=CHECK-NEON
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc -mtriple=armv7-eabi -mattr=-fpregs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-ARM
+; RUN: llc -mtriple=armv7-eabi -mattr=+vfp2 %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-VFP
+; RUN: llc -mtriple=thumbv7-apple-darwin -mattr=+neon,+thumb2 %s -o - | FileCheck %s --check-prefix=CHECK-NEON
define i32 @f1(i32 %a.s) {
-;CHECK-LABEL: f1:
-;CHECK: moveq
+; CHECK-LABEL: f1:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: mov r1, #3
+; CHECK-NEXT: cmp r0, #4
+; CHECK-NEXT: movweq r1, #2
+; CHECK-NEXT: mov r0, r1
+; CHECK-NEXT: bx lr
+;
+; CHECK-NEON-LABEL: f1:
+; CHECK-NEON: @ %bb.0: @ %entry
+; CHECK-NEON-NEXT: movs r1, #3
+; CHECK-NEON-NEXT: cmp r0, #4
+; CHECK-NEON-NEXT: it eq
+; CHECK-NEON-NEXT: moveq r1, #2
+; CHECK-NEON-NEXT: mov r0, r1
+; CHECK-NEON-NEXT: bx lr
entry:
%tmp = icmp eq i32 %a.s, 4
%tmp1.s = select i1 %tmp, i32 2, i32 3
@@ -16,8 +27,22 @@ entry:
}
define i32 @f2(i32 %a.s) {
-;CHECK-LABEL: f2:
-;CHECK: movgt
+; CHECK-LABEL: f2:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: mov r1, #3
+; CHECK-NEXT: cmp r0, #4
+; CHECK-NEXT: movwgt r1, #2
+; CHECK-NEXT: mov r0, r1
+; CHECK-NEXT: bx lr
+;
+; CHECK-NEON-LABEL: f2:
+; CHECK-NEON: @ %bb.0: @ %entry
+; CHECK-NEON-NEXT: movs r1, #3
+; CHECK-NEON-NEXT: cmp r0, #4
+; CHECK-NEON-NEXT: it gt
+; CHECK-NEON-NEXT: movgt r1, #2
+; CHECK-NEON-NEXT: mov r0, r1
+; CHECK-NEON-NEXT: bx lr
entry:
%tmp = icmp sgt i32 %a.s, 4
%tmp1.s = select i1 %tmp, i32 2, i32 3
@@ -25,8 +50,22 @@ entry:
}
define i32 @f3(i32 %a.s, i32 %b.s) {
-;CHECK-LABEL: f3:
-;CHECK: movlt
+; CHECK-LABEL: f3:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: mov r2, #3
+; CHECK-NEXT: cmp r0, r1
+; CHECK-NEXT: movwlt r2, #2
+; CHECK-NEXT: mov r0, r2
+; CHECK-NEXT: bx lr
+;
+; CHECK-NEON-LABEL: f3:
+; CHECK-NEON: @ %bb.0: @ %entry
+; CHECK-NEON-NEXT: movs r2, #3
+; CHECK-NEON-NEXT: cmp r0, r1
+; CHECK-NEON-NEXT: it lt
+; CHECK-NEON-NEXT: movlt r2, #2
+; CHECK-NEON-NEXT: mov r0, r2
+; CHECK-NEON-NEXT: bx lr
entry:
%tmp = icmp slt i32 %a.s, %b.s
%tmp1.s = select i1 %tmp, i32 2, i32 3
@@ -34,8 +73,22 @@ entry:
}
define i32 @f4(i32 %a.s, i32 %b.s) {
-;CHECK-LABEL: f4:
-;CHECK: movle
+; CHECK-LABEL: f4:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: mov r2, #3
+; CHECK-NEXT: cmp r0, r1
+; CHECK-NEXT: movwle r2, #2
+; CHECK-NEXT: mov r0, r2
+; CHECK-NEXT: bx lr
+;
+; CHECK-NEON-LABEL: f4:
+; CHECK-NEON: @ %bb.0: @ %entry
+; CHECK-NEON-NEXT: movs r2, #3
+; CHECK-NEON-NEXT: cmp r0, r1
+; CHECK-NEON-NEXT: it le
+; CHECK-NEON-NEXT: movle r2, #2
+; CHECK-NEON-NEXT: mov r0, r2
+; CHECK-NEON-NEXT: bx lr
entry:
%tmp = icmp sle i32 %a.s, %b.s
%tmp1.s = select i1 %tmp, i32 2, i32 3
@@ -43,8 +96,22 @@ entry:
}
define i32 @f5(i32 %a.u, i32 %b.u) {
-;CHECK-LABEL: f5:
-;CHECK: movls
+; CHECK-LABEL: f5:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: mov r2, #3
+; CHECK-NEXT: cmp r0, r1
+; CHECK-NEXT: movwls r2, #2
+; CHECK-NEXT: mov r0, r2
+; CHECK-NEXT: bx lr
+;
+; CHECK-NEON-LABEL: f5:
+; CHECK-NEON: @ %bb.0: @ %entry
+; CHECK-NEON-NEXT: movs r2, #3
+; CHECK-NEON-NEXT: cmp r0, r1
+; CHECK-NEON-NEXT: it ls
+; CHECK-NEON-NEXT: movls r2, #2
+; CHECK-NEON-NEXT: mov r0, r2
+; CHECK-NEON-NEXT: bx lr
entry:
%tmp = icmp ule i32 %a.u, %b.u
%tmp1.s = select i1 %tmp, i32 2, i32 3
@@ -52,8 +119,22 @@ entry:
}
define i32 @f6(i32 %a.u, i32 %b.u) {
-;CHECK-LABEL: f6:
-;CHECK: movhi
+; CHECK-LABEL: f6:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: mov r2, #3
+; CHECK-NEXT: cmp r0, r1
+; CHECK-NEXT: movwhi r2, #2
+; CHECK-NEXT: mov r0, r2
+; CHECK-NEXT: bx lr
+;
+; CHECK-NEON-LABEL: f6:
+; CHECK-NEON: @ %bb.0: @ %entry
+; CHECK-NEON-NEXT: movs r2, #3
+; CHECK-NEON-NEXT: cmp r0, r1
+; CHECK-NEON-NEXT: it hi
+; CHECK-NEON-NEXT: movhi r2, #2
+; CHECK-NEON-NEXT: mov r0, r2
+; CHECK-NEON-NEXT: bx lr
entry:
%tmp = icmp ugt i32 %a.u, %b.u
%tmp1.s = select i1 %tmp, i32 2, i32 3
@@ -61,11 +142,61 @@ entry:
}
define double @f7(double %a, double %b) {
-;CHECK-LABEL: f7:
-;CHECK: movmi
-;CHECK: movpl
-;CHECK-VFP-LABEL: f7:
-;CHECK-VFP: vmovmi
+; CHECK-ARM-LABEL: f7:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: .save {r4, r5, r11, lr}
+; CHECK-ARM-NEXT: push {r4, r5, r11, lr}
+; CHECK-ARM-NEXT: mov r4, r3
+; CHECK-ARM-NEXT: movw r3, #48758
+; CHECK-ARM-NEXT: mov r5, r2
+; CHECK-ARM-NEXT: movw r2, #14680
+; CHECK-ARM-NEXT: movt r2, #51380
+; CHECK-ARM-NEXT: movt r3, #16371
+; CHECK-ARM-NEXT: bl __aeabi_dcmplt
+; CHECK-ARM-NEXT: cmp r0, #0
+; CHECK-ARM-NEXT: movwne r4, #0
+; CHECK-ARM-NEXT: movwne r5, #0
+; CHECK-ARM-NEXT: movtne r4, #49136
+; CHECK-ARM-NEXT: mov r0, r5
+; CHECK-ARM-NEXT: mov r1, r4
+; CHECK-ARM-NEXT: pop {r4, r5, r11, pc}
+;
+; CHECK-VFP-LABEL: f7:
+; CHECK-VFP: @ %bb.0:
+; CHECK-VFP-NEXT: vldr d17, .LCPI6_0
+; CHECK-VFP-NEXT: vmov d19, r0, r1
+; CHECK-VFP-NEXT: vmov.f64 d16, #-1.000000e+00
+; CHECK-VFP-NEXT: vcmp.f64 d19, d17
+; CHECK-VFP-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-VFP-NEXT: vmov d18, r2, r3
+; CHECK-VFP-NEXT: vmovmi.f64 d18, d16
+; CHECK-VFP-NEXT: vmov r0, r1, d18
+; CHECK-VFP-NEXT: bx lr
+; CHECK-VFP-NEXT: .p2align 3
+; CHECK-VFP-NEXT: @ %bb.1:
+; CHECK-VFP-NEXT: .LCPI6_0:
+; CHECK-VFP-NEXT: .long 3367254360 @ double 1.234
+; CHECK-VFP-NEXT: .long 1072938614
+;
+; CHECK-NEON-LABEL: f7:
+; CHECK-NEON: @ %bb.0:
+; CHECK-NEON-NEXT: vldr d17, LCPI6_0
+; CHECK-NEON-NEXT: vmov d19, r0, r1
+; CHECK-NEON-NEXT: vmov d18, r2, r3
+; CHECK-NEON-NEXT: vcmp.f64 d19, d17
+; CHECK-NEON-NEXT: vmov.f64 d16, #-1.000000e+00
+; CHECK-NEON-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEON-NEXT: it mi
+; CHECK-NEON-NEXT: vmovmi.f64 d18, d16
+; CHECK-NEON-NEXT: vmov r0, r1, d18
+; CHECK-NEON-NEXT: bx lr
+; CHECK-NEON-NEXT: .p2align 3
+; CHECK-NEON-NEXT: @ %bb.1:
+; CHECK-NEON-NEXT: .data_region
+; CHECK-NEON-NEXT: LCPI6_0:
+; CHECK-NEON-NEXT: .long 3367254360 @ double 1.234
+; CHECK-NEON-NEXT: .long 1072938614
+; CHECK-NEON-NEXT: .end_data_region
%tmp = fcmp olt double %a, 1.234e+00
%tmp1 = select i1 %tmp, double -1.000e+00, double %b
ret double %tmp1
@@ -77,18 +208,49 @@ define double @f7(double %a, double %b) {
; a lack of a custom lowering routine for an ISD::SELECT. This would result in
; two "it" blocks in the code: one for the "icmp" and another to move the index
; into the constant pool based on the value of the "icmp". If we have one "it"
-; block generated, odds are good that we have close to the ideal code for this:
+; block generated, odds are good that we have close to the ideal code for this.
+define arm_apcscc float @f8(i32 %a) nounwind {
+; CHECK-ARM-LABEL: f8:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: movw r1, #29905
+; CHECK-ARM-NEXT: movw r2, #1123
+; CHECK-ARM-NEXT: movt r1, #16408
+; CHECK-ARM-NEXT: cmp r0, r2
+; CHECK-ARM-NEXT: movweq r1, #62390
+; CHECK-ARM-NEXT: movteq r1, #16285
+; CHECK-ARM-NEXT: mov r0, r1
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-VFP-LABEL: f8:
+; CHECK-VFP: @ %bb.0:
+; CHECK-VFP-NEXT: movw r2, #1123
+; CHECK-VFP-NEXT: adr r1, .LCPI7_0
+; CHECK-VFP-NEXT: cmp r0, r2
+; CHECK-VFP-NEXT: addeq r1, r1, #4
+; CHECK-VFP-NEXT: ldr r0, [r1]
+; CHECK-VFP-NEXT: bx lr
+; CHECK-VFP-NEXT: .p2align 2
+; CHECK-VFP-NEXT: @ %bb.1:
+; CHECK-VFP-NEXT: .LCPI7_0:
+; CHECK-VFP-NEXT: .long 0x401874d1 @ float 2.38212991
+; CHECK-VFP-NEXT: .long 0x3f9df3b6 @ float 1.23399997
;
; CHECK-NEON-LABEL: f8:
-; CHECK-NEON: adr [[R2:r[0-9]+]], LCPI7_0
-; CHECK-NEON: movw [[R3:r[0-9]+]], #1123
-; CHECK-NEON-NEXT: cmp r0, [[R3]]
-; CHECK-NEON-NEXT: it eq
-; CHECK-NEON-NEXT: addeq{{.*}} [[R2]], #4
-; CHECK-NEON-NEXT: ldr
-; CHECK-NEON: bx
-
-define arm_apcscc float @f8(i32 %a) nounwind {
+; CHECK-NEON: @ %bb.0:
+; CHECK-NEON-NEXT: adr r1, LCPI7_0
+; CHECK-NEON-NEXT: movw r2, #1123
+; CHECK-NEON-NEXT: cmp r0, r2
+; CHECK-NEON-NEXT: it eq
+; CHECK-NEON-NEXT: addeq r1, #4
+; CHECK-NEON-NEXT: ldr r0, [r1]
+; CHECK-NEON-NEXT: bx lr
+; CHECK-NEON-NEXT: .p2align 2
+; CHECK-NEON-NEXT: @ %bb.1:
+; CHECK-NEON-NEXT: .data_region
+; CHECK-NEON-NEXT: LCPI7_0:
+; CHECK-NEON-NEXT: .long 0x401874d1 @ float 2.38212991
+; CHECK-NEON-NEXT: .long 0x3f9df3b6 @ float 1.23399997
+; CHECK-NEON-NEXT: .end_data_region
%tmp = icmp eq i32 %a, 1123
%tmp1 = select i1 %tmp, float 0x3FF3BE76C0000000, float 0x40030E9A20000000
ret float %tmp1
@@ -98,10 +260,40 @@ define arm_apcscc float @f8(i32 %a) nounwind {
; Glue values can only have a single use, but the following test exposed a
; case where a SELECT was lowered with 2 uses of a comparison, causing the
; scheduler to assert.
-; CHECK-VFP-LABEL: f9:
-
declare ptr @objc_msgSend(ptr, ptr, ...)
define void @f9() optsize {
+; CHECK-LABEL: f9:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: .save {r11, lr}
+; CHECK-NEXT: push {r11, lr}
+; CHECK-NEXT: .pad #8
+; CHECK-NEXT: sub sp, sp, #8
+; CHECK-NEXT: movw r2, #0
+; CHECK-NEXT: movw r3, #0
+; CHECK-NEXT: mov r1, #1065353216
+; CHECK-NEXT: mov r0, #0
+; CHECK-NEXT: movt r2, #16672
+; CHECK-NEXT: movt r3, #32704
+; CHECK-NEXT: strd r0, r1, [sp]
+; CHECK-NEXT: bl objc_msgSend
+; CHECK-NEXT: add sp, sp, #8
+; CHECK-NEXT: pop {r11, pc}
+;
+; CHECK-NEON-LABEL: f9:
+; CHECK-NEON: @ %bb.0: @ %entry
+; CHECK-NEON-NEXT: str lr, [sp, #-4]!
+; CHECK-NEON-NEXT: sub sp, #8
+; CHECK-NEON-NEXT: movs r2, #0
+; CHECK-NEON-NEXT: movs r3, #0
+; CHECK-NEON-NEXT: mov.w r0, #1065353216
+; CHECK-NEON-NEXT: movs r1, #0
+; CHECK-NEON-NEXT: movt r2, #16672
+; CHECK-NEON-NEXT: movt r3, #32704
+; CHECK-NEON-NEXT: strd r1, r0, [sp]
+; CHECK-NEON-NEXT: bl _objc_msgSend
+; CHECK-NEON-NEXT: add sp, #8
+; CHECK-NEON-NEXT: ldr lr, [sp], #4
+; CHECK-NEON-NEXT: bx lr
entry:
%cmp = icmp eq ptr undef, inttoptr (i32 4 to ptr)
%conv191 = select i1 %cmp, float -3.000000e+00, float 0.000000e+00
@@ -117,36 +309,151 @@ entry:
ret void
}
-; CHECK-LABEL: f10:
define float @f10(i32 %a, i32 %b) nounwind uwtable readnone ssp {
-; CHECK-NOT: floatsisf
+; CHECK-ARM-LABEL: f10:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: mov r2, #0
+; CHECK-ARM-NEXT: cmp r0, r1
+; CHECK-ARM-NEXT: moveq r2, #1065353216
+; CHECK-ARM-NEXT: mov r0, r2
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-VFP-LABEL: f10:
+; CHECK-VFP: @ %bb.0:
+; CHECK-VFP-NEXT: vmov.f32 s2, #1.000000e+00
+; CHECK-VFP-NEXT: vldr s0, .LCPI9_0
+; CHECK-VFP-NEXT: cmp r0, r1
+; CHECK-VFP-NEXT: vmoveq.f32 s0, s2
+; CHECK-VFP-NEXT: vmov r0, s0
+; CHECK-VFP-NEXT: bx lr
+; CHECK-VFP-NEXT: .p2align 2
+; CHECK-VFP-NEXT: @ %bb.1:
+; CHECK-VFP-NEXT: .LCPI9_0:
+; CHECK-VFP-NEXT: .long 0x00000000 @ float 0
+;
+; CHECK-NEON-LABEL: f10:
+; CHECK-NEON: @ %bb.0:
+; CHECK-NEON-NEXT: vldr s0, LCPI9_0
+; CHECK-NEON-NEXT: vmov.f32 s2, #1.000000e+00
+; CHECK-NEON-NEXT: cmp r0, r1
+; CHECK-NEON-NEXT: it eq
+; CHECK-NEON-NEXT: vmoveq.f32 s0, s2
+; CHECK-NEON-NEXT: vmov r0, s0
+; CHECK-NEON-NEXT: bx lr
+; CHECK-NEON-NEXT: .p2align 2
+; CHECK-NEON-NEXT: @ %bb.1:
+; CHECK-NEON-NEXT: .data_region
+; CHECK-NEON-NEXT: LCPI9_0:
+; CHECK-NEON-NEXT: .long 0x00000000 @ float 0
+; CHECK-NEON-NEXT: .end_data_region
%1 = icmp eq i32 %a, %b
%2 = zext i1 %1 to i32
%3 = sitofp i32 %2 to float
ret float %3
}
-; CHECK-LABEL: f11:
define float @f11(i32 %a, i32 %b) nounwind uwtable readnone ssp {
-; CHECK-NOT: floatsisf
+; CHECK-ARM-LABEL: f11:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: mov r2, #0
+; CHECK-ARM-NEXT: cmp r0, r1
+; CHECK-ARM-NEXT: movweq r2, #0
+; CHECK-ARM-NEXT: movteq r2, #49024
+; CHECK-ARM-NEXT: mov r0, r2
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-VFP-LABEL: f11:
+; CHECK-VFP: @ %bb.0:
+; CHECK-VFP-NEXT: vmov.f32 s2, #-1.000000e+00
+; CHECK-VFP-NEXT: vldr s0, .LCPI10_0
+; CHECK-VFP-NEXT: cmp r0, r1
+; CHECK-VFP-NEXT: vmoveq.f32 s0, s2
+; CHECK-VFP-NEXT: vmov r0, s0
+; CHECK-VFP-NEXT: bx lr
+; CHECK-VFP-NEXT: .p2align 2
+; CHECK-VFP-NEXT: @ %bb.1:
+; CHECK-VFP-NEXT: .LCPI10_0:
+; CHECK-VFP-NEXT: .long 0x00000000 @ float 0
+;
+; CHECK-NEON-LABEL: f11:
+; CHECK-NEON: @ %bb.0:
+; CHECK-NEON-NEXT: vldr s0, LCPI10_0
+; CHECK-NEON-NEXT: vmov.f32 s2, #-1.000000e+00
+; CHECK-NEON-NEXT: cmp r0, r1
+; CHECK-NEON-NEXT: it eq
+; CHECK-NEON-NEXT: vmoveq.f32 s0, s2
+; CHECK-NEON-NEXT: vmov r0, s0
+; CHECK-NEON-NEXT: bx lr
+; CHECK-NEON-NEXT: .p2align 2
+; CHECK-NEON-NEXT: @ %bb.1:
+; CHECK-NEON-NEXT: .data_region
+; CHECK-NEON-NEXT: LCPI10_0:
+; CHECK-NEON-NEXT: .long 0x00000000 @ float 0
+; CHECK-NEON-NEXT: .end_data_region
%1 = icmp eq i32 %a, %b
%2 = sitofp i1 %1 to float
ret float %2
}
-; CHECK-LABEL: f12:
define float @f12(i32 %a, i32 %b) nounwind uwtable readnone ssp {
-; CHECK-NOT: floatunsisf
+; CHECK-ARM-LABEL: f12:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: mov r2, #0
+; CHECK-ARM-NEXT: cmp r0, r1
+; CHECK-ARM-NEXT: moveq r2, #1065353216
+; CHECK-ARM-NEXT: mov r0, r2
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-VFP-LABEL: f12:
+; CHECK-VFP: @ %bb.0:
+; CHECK-VFP-NEXT: vmov.f32 s2, #1.000000e+00
+; CHECK-VFP-NEXT: vldr s0, .LCPI11_0
+; CHECK-VFP-NEXT: cmp r0, r1
+; CHECK-VFP-NEXT: vmoveq.f32 s0, s2
+; CHECK-VFP-NEXT: vmov r0, s0
+; CHECK-VFP-NEXT: bx lr
+; CHECK-VFP-NEXT: .p2align 2
+; CHECK-VFP-NEXT: @ %bb.1:
+; CHECK-VFP-NEXT: .LCPI11_0:
+; CHECK-VFP-NEXT: .long 0x00000000 @ float 0
+;
+; CHECK-NEON-LABEL: f12:
+; CHECK-NEON: @ %bb.0:
+; CHECK-NEON-NEXT: vldr s0, LCPI11_0
+; CHECK-NEON-NEXT: vmov.f32 s2, #1.000000e+00
+; CHECK-NEON-NEXT: cmp r0, r1
+; CHECK-NEON-NEXT: it eq
+; CHECK-NEON-NEXT: vmoveq.f32 s0, s2
+; CHECK-NEON-NEXT: vmov r0, s0
+; CHECK-NEON-NEXT: bx lr
+; CHECK-NEON-NEXT: .p2align 2
+; CHECK-NEON-NEXT: @ %bb.1:
+; CHECK-NEON-NEXT: .data_region
+; CHECK-NEON-NEXT: LCPI11_0:
+; CHECK-NEON-NEXT: .long 0x00000000 @ float 0
+; CHECK-NEON-NEXT: .end_data_region
%1 = icmp eq i32 %a, %b
%2 = uitofp i1 %1 to float
ret float %2
}
-; CHECK-LABEL: test_overflow_recombine:
define i1 @test_overflow_recombine(i32 %in1, i32 %in2) {
-; CHECK: smull [[LO:r[0-9]+]], [[HI:r[0-9]+]]
-; CHECK: subs [[ZERO:r[0-9]+]], [[HI]], [[LO]], asr #31
-; CHECK: movne [[ZERO]], #1
+; CHECK-LABEL: test_overflow_recombine:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: mul r2, r0, r1
+; CHECK-NEXT: smmul r0, r0, r1
+; CHECK-NEXT: subs r0, r0, r2, asr #31
+; CHECK-NEXT: movwne r0, #1
+; CHECK-NEXT: bx lr
+;
+; CHECK-NEON-LABEL: test_overflow_recombine:
+; CHECK-NEON: @ %bb.0:
+; CHECK-NEON-NEXT: mul r2, r0, r1
+; CHECK-NEON-NEXT: smmul r0, r0, r1
+; CHECK-NEON-NEXT: subs.w r0, r0, r2, asr #31
+; CHECK-NEON-NEXT: it ne
+; CHECK-NEON-NEXT: movne r0, #1
+; CHECK-NEON-NEXT: bx lr
%prod = call { i32, i1 } @llvm.smul.with.overflow.i32(i32 %in1, i32 %in2)
%overflow = extractvalue { i32, i1 } %prod, 1
ret i1 %overflow
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