[llvm] [CodeGen][MRI] Introduce synthetic register classes (PR #86006)

[Matt Arsenault via llvm-commits]

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@@ -101,6 +102,9 @@ class MCRegisterClass {
 
   /// Return true if this register class has a defined BaseClassOrder.
   bool isBaseClass() const { return BaseClass; }
+  /// isSynthetic - Return true if this is a synthetic class. This field helps
+  /// targets to dynamically enable the regclass during codegen.
+  bool isSynthetic() const { return Synthetic; }
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arsenm wrote:

We want to express a software constraint. Every other class is expressing a hardware constraint. We want to express a synthetic allocation window 

https://github.com/llvm/llvm-project/pull/86006