[llvm] [NewPM][AMDGPU] Add AMDGPUPassRegistry.def (PR #86095)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 21 00:24:27 PDT 2024
https://github.com/paperchalice updated https://github.com/llvm/llvm-project/pull/86095
>From bc2a45cf18c9e82e44e187de4481742465be2c7c Mon Sep 17 00:00:00 2001
From: PaperChalice <liujunchang97 at outlook.com>
Date: Thu, 21 Mar 2024 14:44:51 +0800
Subject: [PATCH] [NewPM][AMDGPU] Add AMDGPUPassRegistry.def
---
llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def | 73 +++++++++++
.../lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 115 +++---------------
.../AMDGPU/global_atomic_optimizer_fp_rtn.ll | 4 +-
.../global_atomics_iterative_scan_fp.ll | 4 +-
.../global_atomics_optimizer_fp_no_rtn.ll | 4 +-
5 files changed, 96 insertions(+), 104 deletions(-)
create mode 100644 llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
new file mode 100644
index 00000000000000..90f36fadf35903
--- /dev/null
+++ b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
@@ -0,0 +1,73 @@
+//===- AMDGPUPassRegistry.def - Registry of AMDGPU passes -------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file is used as the registry of passes that are part of the
+// AMDGPU backend.
+//
+//===----------------------------------------------------------------------===//
+
+// NOTE: NO INCLUDE GUARD DESIRED!
+
+#ifndef MODULE_PASS
+#define MODULE_PASS(NAME, CREATE_PASS)
+#endif
+MODULE_PASS("amdgpu-always-inline", AMDGPUAlwaysInlinePass())
+MODULE_PASS("amdgpu-attributor", AMDGPUAttributorPass(*this))
+MODULE_PASS("amdgpu-lower-buffer-fat-pointers",
+ AMDGPULowerBufferFatPointersPass(*this))
+MODULE_PASS("amdgpu-lower-ctor-dtor", AMDGPUCtorDtorLoweringPass())
+MODULE_PASS("amdgpu-lower-module-lds", AMDGPULowerModuleLDSPass(*this))
+MODULE_PASS("amdgpu-printf-runtime-binding", AMDGPUPrintfRuntimeBindingPass())
+MODULE_PASS("amdgpu-unify-metadata", AMDGPUUnifyMetadataPass())
+#undef MODULE_PASS
+
+#ifndef FUNCTION_PASS
+#define FUNCTION_PASS(NAME, CREATE_PASS)
+#endif
+FUNCTION_PASS("amdgpu-codegenprepare", AMDGPUCodeGenPreparePass(*this))
+FUNCTION_PASS("amdgpu-image-intrinsic-opt",
+ AMDGPUImageIntrinsicOptimizerPass(*this))
+FUNCTION_PASS("amdgpu-lower-kernel-arguments",
+ AMDGPULowerKernelArgumentsPass(*this))
+FUNCTION_PASS("amdgpu-lower-kernel-attributes",
+ AMDGPULowerKernelAttributesPass())
+FUNCTION_PASS("amdgpu-simplifylib", AMDGPUSimplifyLibCallsPass())
+FUNCTION_PASS("amdgpu-promote-alloca", AMDGPUPromoteAllocaPass(*this))
+FUNCTION_PASS("amdgpu-promote-alloca-to-vector",
+ AMDGPUPromoteAllocaToVectorPass(*this))
+FUNCTION_PASS("amdgpu-promote-kernel-arguments",
+ AMDGPUPromoteKernelArgumentsPass())
+FUNCTION_PASS("amdgpu-rewrite-undef-for-phi", AMDGPURewriteUndefForPHIPass())
+FUNCTION_PASS("amdgpu-unify-divergent-exit-nodes",
+ AMDGPUUnifyDivergentExitNodesPass())
+FUNCTION_PASS("amdgpu-usenative", AMDGPUUseNativeCallsPass())
+#undef FUNCTION_PASS
+
+#ifndef FUNCTION_ANALYSIS
+#define FUNCTION_ANALYSIS(NAME, CREATE_PASS)
+#endif
+
+#ifndef FUNCTION_ALIAS_ANALYSIS
+#define FUNCTION_ALIAS_ANALYSIS(NAME, CREATE_PASS) \
+ FUNCTION_ANALYSIS(NAME, CREATE_PASS)
+#endif
+FUNCTION_ALIAS_ANALYSIS("amdgpu-aa", AMDGPUAA())
+#undef FUNCTION_ALIAS_ANALYSIS
+#undef FUNCTION_ANALYSIS
+
+#ifndef FUNCTION_PASS_WITH_PARAMS
+#define FUNCTION_PASS_WITH_PARAMS(NAME, CLASS, CREATE_PASS, PARSER, PARAMS)
+#endif
+FUNCTION_PASS_WITH_PARAMS(
+ "amdgpu-atomic-optimizer",
+ "AMDGPUAtomicOptimizerPass",
+ [=](ScanOptions Strategy) {
+ return AMDGPUAtomicOptimizerPass(*this, Strategy);
+ },
+ parseAMDGPUAtomicOptimizerStrategy, "strategy=dpp|iterative|none")
+#undef FUNCTION_PASS_WITH_PARAMS
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 2b457fe519d96c..98323d0d28a2e4 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -631,107 +631,26 @@ void AMDGPUTargetMachine::registerDefaultAliasAnalyses(AAManager &AAM) {
AAM.registerFunctionAnalysis<AMDGPUAA>();
}
+static Expected<ScanOptions>
+parseAMDGPUAtomicOptimizerStrategy(StringRef Params) {
+ if (Params.consume_front("strategy=")) {
+ if (Params == "dpp")
+ return ScanOptions::DPP;
+ if (Params == "iterative")
+ return ScanOptions::Iterative;
+ if (Params == "none")
+ return ScanOptions::None;
+ return make_error<StringError>("invalid parameter",
+ inconvertibleErrorCode());
+ }
+ return ScanOptions::Iterative;
+}
+
void AMDGPUTargetMachine::registerPassBuilderCallbacks(
PassBuilder &PB, bool PopulateClassToPassNames) {
- PB.registerPipelineParsingCallback(
- [this](StringRef PassName, ModulePassManager &PM,
- ArrayRef<PassBuilder::PipelineElement>) {
- if (PassName == "amdgpu-attributor") {
- PM.addPass(AMDGPUAttributorPass(*this));
- return true;
- }
- if (PassName == "amdgpu-unify-metadata") {
- PM.addPass(AMDGPUUnifyMetadataPass());
- return true;
- }
- if (PassName == "amdgpu-printf-runtime-binding") {
- PM.addPass(AMDGPUPrintfRuntimeBindingPass());
- return true;
- }
- if (PassName == "amdgpu-always-inline") {
- PM.addPass(AMDGPUAlwaysInlinePass());
- return true;
- }
- if (PassName == "amdgpu-lower-module-lds") {
- PM.addPass(AMDGPULowerModuleLDSPass(*this));
- return true;
- }
- if (PassName == "amdgpu-lower-buffer-fat-pointers") {
- PM.addPass(AMDGPULowerBufferFatPointersPass(*this));
- return true;
- }
- if (PassName == "amdgpu-lower-ctor-dtor") {
- PM.addPass(AMDGPUCtorDtorLoweringPass());
- return true;
- }
- return false;
- });
- PB.registerPipelineParsingCallback(
- [this](StringRef PassName, FunctionPassManager &PM,
- ArrayRef<PassBuilder::PipelineElement>) {
- if (PassName == "amdgpu-simplifylib") {
- PM.addPass(AMDGPUSimplifyLibCallsPass());
- return true;
- }
- if (PassName == "amdgpu-image-intrinsic-opt") {
- PM.addPass(AMDGPUImageIntrinsicOptimizerPass(*this));
- return true;
- }
- if (PassName == "amdgpu-usenative") {
- PM.addPass(AMDGPUUseNativeCallsPass());
- return true;
- }
- if (PassName == "amdgpu-promote-alloca") {
- PM.addPass(AMDGPUPromoteAllocaPass(*this));
- return true;
- }
- if (PassName == "amdgpu-promote-alloca-to-vector") {
- PM.addPass(AMDGPUPromoteAllocaToVectorPass(*this));
- return true;
- }
- if (PassName == "amdgpu-lower-kernel-attributes") {
- PM.addPass(AMDGPULowerKernelAttributesPass());
- return true;
- }
- if (PassName == "amdgpu-promote-kernel-arguments") {
- PM.addPass(AMDGPUPromoteKernelArgumentsPass());
- return true;
- }
- if (PassName == "amdgpu-unify-divergent-exit-nodes") {
- PM.addPass(AMDGPUUnifyDivergentExitNodesPass());
- return true;
- }
- if (PassName == "amdgpu-atomic-optimizer") {
- PM.addPass(
- AMDGPUAtomicOptimizerPass(*this, AMDGPUAtomicOptimizerStrategy));
- return true;
- }
- if (PassName == "amdgpu-codegenprepare") {
- PM.addPass(AMDGPUCodeGenPreparePass(*this));
- return true;
- }
- if (PassName == "amdgpu-lower-kernel-arguments") {
- PM.addPass(AMDGPULowerKernelArgumentsPass(*this));
- return true;
- }
- if (PassName == "amdgpu-rewrite-undef-for-phi") {
- PM.addPass(AMDGPURewriteUndefForPHIPass());
- return true;
- }
- return false;
- });
-
- PB.registerAnalysisRegistrationCallback([](FunctionAnalysisManager &FAM) {
- FAM.registerPass([&] { return AMDGPUAA(); });
- });
- PB.registerParseAACallback([](StringRef AAName, AAManager &AAM) {
- if (AAName == "amdgpu-aa") {
- AAM.registerFunctionAnalysis<AMDGPUAA>();
- return true;
- }
- return false;
- });
+#define GET_PASS_REGISTRY "AMDGPUPassRegistry.def"
+#include "llvm/Passes/TargetPassRegistry.inc"
PB.registerPipelineStartEPCallback(
[](ModulePassManager &PM, OptimizationLevel Level) {
diff --git a/llvm/test/CodeGen/AMDGPU/global_atomic_optimizer_fp_rtn.ll b/llvm/test/CodeGen/AMDGPU/global_atomic_optimizer_fp_rtn.ll
index 538ef42121b83b..b7a91f6fa96dc4 100644
--- a/llvm/test/CodeGen/AMDGPU/global_atomic_optimizer_fp_rtn.ll
+++ b/llvm/test/CodeGen/AMDGPU/global_atomic_optimizer_fp_rtn.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -S -mtriple=amdgcn-- -mcpu=gfx906 -amdgpu-atomic-optimizer-strategy=Iterative -passes='amdgpu-atomic-optimizer,verify<domtree>' %s | FileCheck --check-prefixes=IR,IR-ITERATIVE %s
-; RUN: opt -S -mtriple=amdgcn-- -mcpu=gfx906 -amdgpu-atomic-optimizer-strategy=DPP -passes='amdgpu-atomic-optimizer,verify<domtree>' %s | FileCheck --check-prefixes=IR,IR-DPP %s
+; RUN: opt -S -mtriple=amdgcn-- -mcpu=gfx906 -passes='amdgpu-atomic-optimizer<strategy=iterative>,verify<domtree>' %s | FileCheck --check-prefixes=IR,IR-ITERATIVE %s
+; RUN: opt -S -mtriple=amdgcn-- -mcpu=gfx906 -passes='amdgpu-atomic-optimizer<strategy=dpp>,verify<domtree>' %s | FileCheck --check-prefixes=IR,IR-DPP %s
; Tests various combinations of uniform/divergent address and uniform/divergent value inputs of various types for atomic operations.
; Optimization remains same for Iterative and DPP strategies when value in uniform. These different scan/reduction
diff --git a/llvm/test/CodeGen/AMDGPU/global_atomics_iterative_scan_fp.ll b/llvm/test/CodeGen/AMDGPU/global_atomics_iterative_scan_fp.ll
index fab24e10f810ff..86e3d9338e0780 100644
--- a/llvm/test/CodeGen/AMDGPU/global_atomics_iterative_scan_fp.ll
+++ b/llvm/test/CodeGen/AMDGPU/global_atomics_iterative_scan_fp.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -S -mtriple=amdgcn-- -amdgpu-atomic-optimizer-strategy=Iterative -passes='amdgpu-atomic-optimizer,verify<domtree>' %s | FileCheck -check-prefix=IR-ITERATIVE %s
-; RUN: opt -S -mtriple=amdgcn-- -amdgpu-atomic-optimizer-strategy=DPP -passes='amdgpu-atomic-optimizer,verify<domtree>' %s | FileCheck -check-prefix=IR-DPP %s
+; RUN: opt -S -mtriple=amdgcn-- -passes='amdgpu-atomic-optimizer<strategy=iterative>,verify<domtree>' %s | FileCheck -check-prefix=IR-ITERATIVE %s
+; RUN: opt -S -mtriple=amdgcn-- -passes='amdgpu-atomic-optimizer<strategy=dpp>,verify<domtree>' %s | FileCheck -check-prefix=IR-DPP %s
declare i32 @llvm.amdgcn.workitem.id.x()
define amdgpu_kernel void @global_atomic_fadd_uni_value(ptr addrspace(1) %ptr) #0 {
; IR-ITERATIVE-LABEL: @global_atomic_fadd_uni_value(
diff --git a/llvm/test/CodeGen/AMDGPU/global_atomics_optimizer_fp_no_rtn.ll b/llvm/test/CodeGen/AMDGPU/global_atomics_optimizer_fp_no_rtn.ll
index cc7a45cbb6e374..e70d7347890fe0 100644
--- a/llvm/test/CodeGen/AMDGPU/global_atomics_optimizer_fp_no_rtn.ll
+++ b/llvm/test/CodeGen/AMDGPU/global_atomics_optimizer_fp_no_rtn.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -S -mtriple=amdgcn-- -mcpu=gfx906 -amdgpu-atomic-optimizer-strategy=Iterative -passes='amdgpu-atomic-optimizer,verify<domtree>' %s | FileCheck --check-prefixes=IR,IR-ITERATIVE %s
-; RUN: opt -S -mtriple=amdgcn-- -mcpu=gfx906 -amdgpu-atomic-optimizer-strategy=DPP -passes='amdgpu-atomic-optimizer,verify<domtree>' %s | FileCheck --check-prefixes=IR,IR-DPP %s
+; RUN: opt -S -mtriple=amdgcn-- -mcpu=gfx906 -passes='amdgpu-atomic-optimizer<strategy=iterative>,verify<domtree>' %s | FileCheck --check-prefixes=IR,IR-ITERATIVE %s
+; RUN: opt -S -mtriple=amdgcn-- -mcpu=gfx906 -passes='amdgpu-atomic-optimizer<strategy=dpp>,verify<domtree>' %s | FileCheck --check-prefixes=IR,IR-DPP %s
; Tests various combinations of uniform/divergent address and uniform/divergent value inputs of various types for atomic operations.
; Optimization remains same for Iterative and DPP strategies when value in uniform. These different scan/reduction
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