[llvm] [AMDGPU] Add synthetic regclass WWM_VGPR_32 for wwm reg operands (PR #86008)

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git-clang-format --diff 1f1f569b29f42161ea978328aea60044f16eee49 745b6d377f03b343ad586f7488d9a7571f088bbd -- llvm/include/llvm/CodeGen/LiveStacks.h llvm/include/llvm/CodeGen/MachineInstr.h llvm/include/llvm/CodeGen/MachineRegisterInfo.h llvm/include/llvm/CodeGen/RegisterBankInfo.h llvm/include/llvm/CodeGen/TargetLowering.h llvm/include/llvm/CodeGen/TargetRegisterInfo.h llvm/include/llvm/MC/MCRegisterInfo.h llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp llvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp llvm/lib/CodeGen/AsmPrinter/DwarfExpression.h llvm/lib/CodeGen/DetectDeadLanes.cpp llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp llvm/lib/CodeGen/GlobalISel/Utils.cpp llvm/lib/CodeGen/LiveStacks.cpp llvm/lib/CodeGen/MIRParser/MIRParser.cpp llvm/lib/CodeGen/MachineCSE.cpp llvm/lib/CodeGen/MachineCombiner.cpp llvm/lib/CodeGen/MachineInstr.cpp llvm/lib/CodeGen/MachineRegisterInfo.cpp llvm/lib/CodeGen/MachineVerifier.cpp llvm/lib/CodeGen/PeepholeOptimizer.cpp llvm/lib/CodeGen/PrologEpilogInserter.cpp llvm/lib/CodeGen/RegAllocGreedy.cpp llvm/lib/CodeGen/RegisterBank.cpp llvm/lib/CodeGen/RegisterBankInfo.cpp llvm/lib/CodeGen/RegisterClassInfo.cpp llvm/lib/CodeGen/RegisterCoalescer.cpp llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp llvm/lib/CodeGen/StackMaps.cpp llvm/lib/CodeGen/TailDuplicator.cpp llvm/lib/CodeGen/TargetLoweringBase.cpp llvm/lib/CodeGen/TargetRegisterInfo.cpp llvm/lib/CodeGen/TwoAddressInstructionPass.cpp llvm/lib/Target/AArch64/AArch64FrameLowering.cpp llvm/lib/Target/AArch64/AArch64InstrInfo.cpp llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.cpp llvm/lib/Target/AMDGPU/SIISelLowering.cpp llvm/lib/Target/AMDGPU/SIISelLowering.h llvm/lib/Target/AMDGPU/SIInstrInfo.cpp llvm/lib/Target/AMDGPU/SIInstrInfo.h llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp llvm/lib/Target/AMDGPU/SILowerWWMCopies.cpp llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp llvm/lib/Target/AMDGPU/SIRegisterInfo.h llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp llvm/lib/Target/ARM/ARMBaseRegisterInfo.h llvm/lib/Target/AVR/AVRAsmPrinter.cpp llvm/lib/Target/AVR/AVRFrameLowering.cpp llvm/lib/Target/CSKY/CSKYFrameLowering.cpp llvm/lib/Target/Hexagon/BitTracker.cpp llvm/lib/Target/Hexagon/HexagonBitTracker.cpp llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp llvm/lib/Target/Hexagon/RDFCopy.cpp llvm/lib/Target/LoongArch/LoongArchFrameLowering.cpp llvm/lib/Target/Mips/MipsFrameLowering.cpp llvm/lib/Target/Mips/MipsSEFrameLowering.cpp llvm/lib/Target/PowerPC/PPCFrameLowering.cpp llvm/lib/Target/PowerPC/PPCInstrInfo.cpp llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp llvm/lib/Target/RISCV/RISCVFrameLowering.cpp llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp llvm/lib/Target/WebAssembly/WebAssemblyReplacePhysRegs.cpp llvm/lib/Target/X86/X86FrameLowering.cpp llvm/lib/Target/X86/X86InstrInfo.cpp llvm/lib/Target/X86/X86RegisterInfo.cpp llvm/lib/Target/X86/X86RegisterInfo.h llvm/lib/Target/XCore/XCoreFrameLowering.cpp llvm/unittests/CodeGen/MFCommon.inc llvm/unittests/CodeGen/MachineInstrTest.cpp llvm/utils/TableGen/CodeGenRegisters.cpp llvm/utils/TableGen/CodeGenRegisters.h llvm/utils/TableGen/RegisterInfoEmitter.cpp
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View the diff from clang-format here.
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diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 982d1a0c44..25b0f5688a 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -9738,11 +9738,10 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
           Register TiedReg = R->getReg();
           MVT RegVT = R->getSimpleValueType(0);
           const TargetRegisterClass *RC =
-              TiedReg.isVirtual()
-                  ? MRI.getRegClass(TiedReg)
-                  : RegVT != MVT::Untyped
-                        ? TLI.getRegClassFor(RegVT)
-                        : TRI.getMinimalPhysRegClass(TiedReg, MRI);
+              TiedReg.isVirtual() ? MRI.getRegClass(TiedReg)
+              : RegVT != MVT::Untyped
+                  ? TLI.getRegClassFor(RegVT)
+                  : TRI.getMinimalPhysRegClass(TiedReg, MRI);
           for (unsigned i = 0, e = Flag.getNumOperandRegisters(); i != e; ++i)
             Regs.push_back(MRI.createVirtualRegister(RC));
 
diff --git a/llvm/unittests/CodeGen/MFCommon.inc b/llvm/unittests/CodeGen/MFCommon.inc
index 8db39e384d..7bf78ab41a 100644
--- a/llvm/unittests/CodeGen/MFCommon.inc
+++ b/llvm/unittests/CodeGen/MFCommon.inc
@@ -19,11 +19,7 @@ public:
 
 // Dummy regclass fields ...
 namespace {
-enum {
-  NoRegister,
-  GPR0 = 1,
-  NUM_TARGET_REGS
-};
+enum { NoRegister, GPR0 = 1, NUM_TARGET_REGS };
 
 enum {
   GPRsRegClassID = 0,
@@ -31,16 +27,17 @@ enum {
 
 const MCPhysReg GPRs[] = {GPR0};
 
-const uint8_t GPRsBits[] = { 0x00 };
+const uint8_t GPRsBits[] = {0x00};
 
 static const uint32_t GPRsSubClassMask[] = {
-  0x00000001,
+    0x00000001,
 };
 } // namespace
 
-static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
-static const MCRegisterClass BogusMCRegisterClasses[] = {{ GPRs, GPRsBits, 0, 1,
-    sizeof(GPRsBits), GPRsRegClassID, 1, -1, false, true ,false }};
+static const TargetRegisterClass *const NullRegClasses[] = {nullptr};
+static const MCRegisterClass BogusMCRegisterClasses[] = {
+    {GPRs, GPRsBits, 0, 1, sizeof(GPRsBits), GPRsRegClassID, 1, -1, false, true,
+     false}};
 static const TargetRegisterClass GPRsRegClass = {
     &BogusMCRegisterClasses[GPRsRegClassID],
     GPRsSubClassMask,
@@ -52,16 +49,17 @@ static const TargetRegisterClass GPRsRegClass = {
     false,
     false,
     NullRegClasses,
-    nullptr
-};
+    nullptr};
 
- static const TargetRegisterClass *const BogusRegisterClasses[] = {&GPRsRegClass};
+static const TargetRegisterClass *const BogusRegisterClasses[] = {
+    &GPRsRegClass};
 
 class BogusRegisterInfo : public TargetRegisterInfo {
 public:
   BogusRegisterInfo()
-      : TargetRegisterInfo(nullptr, BogusRegisterClasses, BogusRegisterClasses+1,
-                           nullptr, nullptr, LaneBitmask(~0u), nullptr, nullptr) {
+      : TargetRegisterInfo(nullptr, BogusRegisterClasses,
+                           BogusRegisterClasses + 1, nullptr, nullptr,
+                           LaneBitmask(~0u), nullptr, nullptr) {
     InitMCRegisterInfo(nullptr, 0, 0, 0, nullptr, 0, nullptr, 0, nullptr,
                        nullptr, nullptr, nullptr, nullptr, 0, nullptr, nullptr);
   }

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https://github.com/llvm/llvm-project/pull/86008