[llvm] [RISCV] Add missing feature predicates to some of the RVV pseudos (PR #85983)
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Wed Mar 20 11:24:19 PDT 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: Min-Yih Hsu (mshockwave)
<details>
<summary>Changes</summary>
Some of the RVV pseudos are missing HasVInstructions. This is effectively a NFC.
---
Full diff: https://github.com/llvm/llvm-project/pull/85983.diff
1 Files Affected:
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td (+4-1)
``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index ae93bf69487565..8be4c7741ca12b 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -6698,6 +6698,7 @@ defm PseudoVFWREDOSUM : VPseudoVFWREDO_VS_RM;
// 15. Vector Mask Instructions
//===----------------------------------------------------------------------===//
+let Predicates = [HasVInstructions] in {
//===----------------------------------------------------------------------===//
// 15.1 Vector Mask-Register Logical Instructions
//===----------------------------------------------------------------------===//
@@ -6718,7 +6719,6 @@ defm PseudoVMSET : VPseudoNullaryPseudoM<"VMXNOR">;
//===----------------------------------------------------------------------===//
// 15.2. Vector mask population count vcpop
//===----------------------------------------------------------------------===//
-
let IsSignExtendingOpW = 1 in
defm PseudoVCPOP: VPseudoVPOP_M;
@@ -6753,6 +6753,7 @@ defm PseudoVIOTA_M: VPseudoVIOTA_M;
// 15.9. Vector Element Index Instruction
//===----------------------------------------------------------------------===//
defm PseudoVID : VPseudoVID_V;
+} // Predicates = [HasVInstructions]
//===----------------------------------------------------------------------===//
// 16. Vector Permutation Instructions
@@ -6828,6 +6829,7 @@ let Predicates = [HasVInstructionsAnyF] in {
//===----------------------------------------------------------------------===//
// 16.4. Vector Register Gather Instructions
//===----------------------------------------------------------------------===//
+let Predicates = [HasVInstructions] in {
defm PseudoVRGATHER : VPseudoVGTR_VV_VX_VI<uimm5, "@earlyclobber $rd">;
defm PseudoVRGATHEREI16 : VPseudoVGTR_VV_EEW<eew=16,
Constraint="@earlyclobber $rd">;
@@ -6836,6 +6838,7 @@ defm PseudoVRGATHEREI16 : VPseudoVGTR_VV_EEW<eew=16,
// 16.5. Vector Compress Instruction
//===----------------------------------------------------------------------===//
defm PseudoVCOMPRESS : VPseudoVCPR_V;
+} // Predicates = [HasVInstructions]
//===----------------------------------------------------------------------===//
// Patterns.
``````````
</details>
https://github.com/llvm/llvm-project/pull/85983
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