[llvm] 5e6bb1f - [TableGen][Target] Add documentation to `Constraints`. (#85951)

[via llvm-commits]

Author: Jason Eckhardt
Date: 2024-03-20T12:56:49-05:00
New Revision: 5e6bb1fb885abec2e8bc85422bbd83fe4ece6d3b

URL: https://github.com/llvm/llvm-project/commit/5e6bb1fb885abec2e8bc85422bbd83fe4ece6d3b
DIFF: https://github.com/llvm/llvm-project/commit/5e6bb1fb885abec2e8bc85422bbd83fe4ece6d3b.diff

LOG: [TableGen][Target] Add documentation to `Constraints`. (#85951)

This patch adds some basic documentation for `Constraints`, along with
some "see also" pointers for backend writers to learn more.

Added: 
    

Modified: 
    llvm/include/llvm/Target/Target.td

Removed: 
    


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diff  --git a/llvm/include/llvm/Target/Target.td b/llvm/include/llvm/Target/Target.td
index 1e40cc49040d6f..cb1c0ed2513d45 100644
--- a/llvm/include/llvm/Target/Target.td
+++ b/llvm/include/llvm/Target/Target.td
@@ -697,7 +697,20 @@ class Instruction : InstructionEncoding {
   // Scheduling information from TargetSchedule.td.
   list<SchedReadWrite> SchedRW;
 
-  string Constraints = "";  // OperandConstraint, e.g. $src = $dst.
+  /// Support for operand constraints. There are currently two kinds:
+  /// "$src = $dst"
+  ///   Ensures that the operands are allocated to the same register.
+  ///
+  /// "@earlyclobber $rd"
+  ///   Ensures that LLVM will not use the same register for any inputs (other
+  ///   than an input tied to this output).
+  ///
+  /// See also:
+  /// - MC/MCInstrDesc.h:OperandConstraint::{TIED_TO, EARLY_CLOBBER}.
+  /// - CodeGen/MachineOperand.h:MachineOperand::{TiedTo, IsEarlyClobber}.
+  /// - The LLVM IR specification: Section `Output constraints` in the
+  ///   discussion of inline assembly constraint strings.
+  string Constraints = "";
 
   /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not
   /// be encoded into the output machineinstr.