[llvm] [CodeGen] Make the parameter TRI required in some functions. (PR #85968)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 20 10:12:20 PDT 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-webassembly
@llvm/pr-subscribers-backend-risc-v
Author: Xu Zhang (simonzgx)
<details>
<summary>Changes</summary>
Make the parameter TRI required in some functions to prevent miscalling.
---
Patch is 127.03 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/85968.diff
82 Files Affected:
- (modified) llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h (+1-1)
- (modified) llvm/include/llvm/CodeGen/MachineInstr.h (+34-38)
- (modified) llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp (+5-4)
- (modified) llvm/lib/CodeGen/CalcSpillWeights.cpp (+2-1)
- (modified) llvm/lib/CodeGen/CodeGenCommonISel.cpp (+1-1)
- (modified) llvm/lib/CodeGen/EarlyIfConversion.cpp (+2-2)
- (modified) llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp (+1-1)
- (modified) llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp (+2-2)
- (modified) llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp (+2-1)
- (modified) llvm/lib/CodeGen/InlineSpiller.cpp (+1-1)
- (modified) llvm/lib/CodeGen/LiveVariables.cpp (+6-5)
- (modified) llvm/lib/CodeGen/MachineCSE.cpp (+1-1)
- (modified) llvm/lib/CodeGen/MachineCombiner.cpp (+8-6)
- (modified) llvm/lib/CodeGen/MachineCopyPropagation.cpp (+1-1)
- (modified) llvm/lib/CodeGen/MachineInstr.cpp (+7-6)
- (modified) llvm/lib/CodeGen/MachineLateInstrsCleanup.cpp (+1-1)
- (modified) llvm/lib/CodeGen/MachineSink.cpp (+1-1)
- (modified) llvm/lib/CodeGen/ModuloSchedule.cpp (+5-4)
- (modified) llvm/lib/CodeGen/PHIElimination.cpp (+7-6)
- (modified) llvm/lib/CodeGen/PeepholeOptimizer.cpp (+1-1)
- (modified) llvm/lib/CodeGen/RegisterCoalescer.cpp (+2-2)
- (modified) llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp (+1-1)
- (modified) llvm/lib/CodeGen/StackSlotColoring.cpp (+1-1)
- (modified) llvm/lib/CodeGen/TwoAddressInstructionPass.cpp (+9-7)
- (modified) llvm/lib/Target/AArch64/AArch64ConditionOptimizer.cpp (+1-1)
- (modified) llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp (+1-1)
- (modified) llvm/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp (+2-1)
- (modified) llvm/lib/Target/AArch64/AArch64InstrInfo.cpp (+18-15)
- (modified) llvm/lib/Target/AArch64/AArch64MacroFusion.cpp (+2-2)
- (modified) llvm/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp (+1-1)
- (modified) llvm/lib/Target/AArch64/GISel/AArch64PostSelectOptimize.cpp (+2-2)
- (modified) llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp (+4-3)
- (modified) llvm/lib/Target/AMDGPU/R600InstrInfo.cpp (+2-2)
- (modified) llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp (+2-2)
- (modified) llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp (+3-3)
- (modified) llvm/lib/Target/AMDGPU/SIInstrInfo.cpp (+9-9)
- (modified) llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp (+1-1)
- (modified) llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp (+2-2)
- (modified) llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp (+5-5)
- (modified) llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp (+1-1)
- (modified) llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp (+2-2)
- (modified) llvm/lib/Target/ARM/A15SDOptimizer.cpp (+2-2)
- (modified) llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp (+7-7)
- (modified) llvm/lib/Target/ARM/ARMConstantIslandPass.cpp (+1-1)
- (modified) llvm/lib/Target/ARM/ARMFrameLowering.cpp (+1-1)
- (modified) llvm/lib/Target/ARM/ARMISelLowering.cpp (+3-3)
- (modified) llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp (+8-6)
- (modified) llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp (+4-3)
- (modified) llvm/lib/Target/ARM/MVETPAndVPTOptimisationsPass.cpp (+9-8)
- (modified) llvm/lib/Target/ARM/MVEVPTBlockPass.cpp (+2-1)
- (modified) llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp (+1-1)
- (modified) llvm/lib/Target/ARM/Thumb2InstrInfo.cpp (+1-1)
- (modified) llvm/lib/Target/ARM/Thumb2SizeReduction.cpp (+3-3)
- (modified) llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp (+4-3)
- (modified) llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp (+5-3)
- (modified) llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp (+3-3)
- (modified) llvm/lib/Target/M68k/M68kISelLowering.cpp (+2-2)
- (modified) llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp (+2-1)
- (modified) llvm/lib/Target/Mips/MipsInstrInfo.cpp (+2-2)
- (modified) llvm/lib/Target/PowerPC/PPCCTRLoops.cpp (+6-3)
- (modified) llvm/lib/Target/PowerPC/PPCInstrInfo.cpp (+9-8)
- (modified) llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp (+2-2)
- (modified) llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp (+6-6)
- (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+1-1)
- (modified) llvm/lib/Target/RISCV/RISCVInsertReadWriteCSR.cpp (+3-2)
- (modified) llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp (+9-6)
- (modified) llvm/lib/Target/RISCV/RISCVInsertWriteVXRM.cpp (+4-2)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.cpp (+3-3)
- (modified) llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp (+1-1)
- (modified) llvm/lib/Target/SystemZ/SystemZElimCompare.cpp (+3-3)
- (modified) llvm/lib/Target/SystemZ/SystemZISelLowering.cpp (+8-7)
- (modified) llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp (+9-9)
- (modified) llvm/lib/Target/WebAssembly/WebAssemblyDebugValueManager.cpp (+1-1)
- (modified) llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp (+5-5)
- (modified) llvm/lib/Target/X86/X86CmovConversion.cpp (+4-4)
- (modified) llvm/lib/Target/X86/X86FixupSetCC.cpp (+2-2)
- (modified) llvm/lib/Target/X86/X86FlagsCopyLowering.cpp (+9-7)
- (modified) llvm/lib/Target/X86/X86FloatingPoint.cpp (+16-15)
- (modified) llvm/lib/Target/X86/X86ISelLowering.cpp (+8-8)
- (modified) llvm/lib/Target/X86/X86InstrInfo.cpp (+22-16)
- (modified) llvm/lib/Target/X86/X86MCInstLower.cpp (+2-1)
- (modified) llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp (+9-6)
``````````diff
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h b/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
index ca62f38061b115..58a200b16ddee1 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
@@ -906,7 +906,7 @@ class LegalizationArtifactCombiner {
unsigned &DefOperandIdx) {
if (Register Def = findValueFromDefImpl(Reg, 0, Size)) {
if (auto *Unmerge = dyn_cast<GUnmerge>(MRI.getVRegDef(Def))) {
- DefOperandIdx = Unmerge->findRegisterDefOperandIdx(Def);
+ DefOperandIdx = Unmerge->findRegisterDefOperandIdx(Def, nullptr);
return Unmerge;
}
}
diff --git a/llvm/include/llvm/CodeGen/MachineInstr.h b/llvm/include/llvm/CodeGen/MachineInstr.h
index fcdd73d8b65fdd..69604292f5cd1b 100644
--- a/llvm/include/llvm/CodeGen/MachineInstr.h
+++ b/llvm/include/llvm/CodeGen/MachineInstr.h
@@ -1443,9 +1443,8 @@ class MachineInstr
/// is a read of a super-register.
/// This does not count partial redefines of virtual registers as reads:
/// %reg1024:6 = OP.
- bool readsRegister(Register Reg,
- const TargetRegisterInfo *TRI = nullptr) const {
- return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
+ bool readsRegister(Register Reg, const TargetRegisterInfo *TRI) const {
+ return findRegisterUseOperandIdx(Reg, TRI, false) != -1;
}
/// Return true if the MachineInstr reads the specified virtual register.
@@ -1464,34 +1463,30 @@ class MachineInstr
/// Return true if the MachineInstr kills the specified register.
/// If TargetRegisterInfo is non-null, then it also checks if there is
/// a kill of a super-register.
- bool killsRegister(Register Reg,
- const TargetRegisterInfo *TRI = nullptr) const {
- return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
+ bool killsRegister(Register Reg, const TargetRegisterInfo *TRI) const {
+ return findRegisterUseOperandIdx(Reg, TRI, true) != -1;
}
/// Return true if the MachineInstr fully defines the specified register.
/// If TargetRegisterInfo is non-null, then it also checks
/// if there is a def of a super-register.
/// NOTE: It's ignoring subreg indices on virtual registers.
- bool definesRegister(Register Reg,
- const TargetRegisterInfo *TRI = nullptr) const {
- return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
+ bool definesRegister(Register Reg, const TargetRegisterInfo *TRI) const {
+ return findRegisterDefOperandIdx(Reg, TRI, false, false) != -1;
}
/// Return true if the MachineInstr modifies (fully define or partially
/// define) the specified register.
/// NOTE: It's ignoring subreg indices on virtual registers.
- bool modifiesRegister(Register Reg,
- const TargetRegisterInfo *TRI = nullptr) const {
- return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
+ bool modifiesRegister(Register Reg, const TargetRegisterInfo *TRI) const {
+ return findRegisterDefOperandIdx(Reg, TRI, false, true) != -1;
}
/// Returns true if the register is dead in this machine instruction.
/// If TargetRegisterInfo is non-null, then it also checks
/// if there is a dead def of a super-register.
- bool registerDefIsDead(Register Reg,
- const TargetRegisterInfo *TRI = nullptr) const {
- return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
+ bool registerDefIsDead(Register Reg, const TargetRegisterInfo *TRI) const {
+ return findRegisterDefOperandIdx(Reg, TRI, true, false) != -1;
}
/// Returns true if the MachineInstr has an implicit-use operand of exactly
@@ -1501,22 +1496,23 @@ class MachineInstr
/// Returns the operand index that is a use of the specific register or -1
/// if it is not found. It further tightens the search criteria to a use
/// that kills the register if isKill is true.
- int findRegisterUseOperandIdx(Register Reg, bool isKill = false,
- const TargetRegisterInfo *TRI = nullptr) const;
+ int findRegisterUseOperandIdx(Register Reg, const TargetRegisterInfo *TRI,
+ bool isKill = false) const;
/// Wrapper for findRegisterUseOperandIdx, it returns
/// a pointer to the MachineOperand rather than an index.
- MachineOperand *findRegisterUseOperand(Register Reg, bool isKill = false,
- const TargetRegisterInfo *TRI = nullptr) {
- int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
+ MachineOperand *findRegisterUseOperand(Register Reg,
+ const TargetRegisterInfo *TRI,
+ bool isKill = false) {
+ int Idx = findRegisterUseOperandIdx(Reg, TRI, isKill);
return (Idx == -1) ? nullptr : &getOperand(Idx);
}
- const MachineOperand *findRegisterUseOperand(
- Register Reg, bool isKill = false,
- const TargetRegisterInfo *TRI = nullptr) const {
- return const_cast<MachineInstr *>(this)->
- findRegisterUseOperand(Reg, isKill, TRI);
+ const MachineOperand *findRegisterUseOperand(Register Reg,
+ const TargetRegisterInfo *TRI,
+ bool isKill = false) const {
+ return const_cast<MachineInstr *>(this)->findRegisterUseOperand(Reg, TRI,
+ isKill);
}
/// Returns the operand index that is a def of the specified register or
@@ -1525,26 +1521,26 @@ class MachineInstr
/// overlap the specified register. If TargetRegisterInfo is non-null,
/// then it also checks if there is a def of a super-register.
/// This may also return a register mask operand when Overlap is true.
- int findRegisterDefOperandIdx(Register Reg,
- bool isDead = false, bool Overlap = false,
- const TargetRegisterInfo *TRI = nullptr) const;
+ int findRegisterDefOperandIdx(Register Reg, const TargetRegisterInfo *TRI,
+ bool isDead = false,
+ bool Overlap = false) const;
/// Wrapper for findRegisterDefOperandIdx, it returns
/// a pointer to the MachineOperand rather than an index.
- MachineOperand *
- findRegisterDefOperand(Register Reg, bool isDead = false,
- bool Overlap = false,
- const TargetRegisterInfo *TRI = nullptr) {
- int Idx = findRegisterDefOperandIdx(Reg, isDead, Overlap, TRI);
+ MachineOperand *findRegisterDefOperand(Register Reg,
+ const TargetRegisterInfo *TRI,
+ bool isDead = false,
+ bool Overlap = false) {
+ int Idx = findRegisterDefOperandIdx(Reg, TRI, isDead, Overlap);
return (Idx == -1) ? nullptr : &getOperand(Idx);
}
- const MachineOperand *
- findRegisterDefOperand(Register Reg, bool isDead = false,
- bool Overlap = false,
- const TargetRegisterInfo *TRI = nullptr) const {
+ const MachineOperand *findRegisterDefOperand(Register Reg,
+ const TargetRegisterInfo *TRI,
+ bool isDead = false,
+ bool Overlap = false) const {
return const_cast<MachineInstr *>(this)->findRegisterDefOperand(
- Reg, isDead, Overlap, TRI);
+ Reg, TRI, isDead, Overlap);
}
/// Find the index of the first operand in the
diff --git a/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp b/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp
index ed6ce6bc73d38c..7c219a91acdb8d 100644
--- a/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp
+++ b/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp
@@ -231,9 +231,9 @@ bool AggressiveAntiDepBreaker::IsImplicitDefUse(MachineInstr &MI,
MachineOperand *Op = nullptr;
if (MO.isDef())
- Op = MI.findRegisterUseOperand(Reg, true);
+ Op = MI.findRegisterUseOperand(Reg, nullptr, true);
else
- Op = MI.findRegisterDefOperand(Reg);
+ Op = MI.findRegisterDefOperand(Reg, nullptr);
return(Op && Op->isImplicit());
}
@@ -679,7 +679,7 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
// defines 'NewReg' via an early-clobber operand.
for (const auto &Q : make_range(RegRefs.equal_range(Reg))) {
MachineInstr *UseMI = Q.second.Operand->getParent();
- int Idx = UseMI->findRegisterDefOperandIdx(NewReg, false, true, TRI);
+ int Idx = UseMI->findRegisterDefOperandIdx(NewReg, TRI, false, true);
if (Idx == -1)
continue;
@@ -846,7 +846,8 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies(
continue;
} else {
// No anti-dep breaking for implicit deps
- MachineOperand *AntiDepOp = MI.findRegisterDefOperand(AntiDepReg);
+ MachineOperand *AntiDepOp =
+ MI.findRegisterDefOperand(AntiDepReg, nullptr);
assert(AntiDepOp && "Can't find index for defined register operand");
if (!AntiDepOp || AntiDepOp->isImplicit()) {
LLVM_DEBUG(dbgs() << " (implicit)\n");
diff --git a/llvm/lib/CodeGen/CalcSpillWeights.cpp b/llvm/lib/CodeGen/CalcSpillWeights.cpp
index f3cb7fa5af6148..6eebc1fc5ca8ce 100644
--- a/llvm/lib/CodeGen/CalcSpillWeights.cpp
+++ b/llvm/lib/CodeGen/CalcSpillWeights.cpp
@@ -251,7 +251,8 @@ float VirtRegAuxInfo::weightCalcHelper(LiveInterval &LI, SlotIndex *Start,
// For terminators that produce values, ask the backend if the register is
// not spillable.
- if (TII.isUnspillableTerminator(MI) && MI->definesRegister(LI.reg())) {
+ if (TII.isUnspillableTerminator(MI) &&
+ MI->definesRegister(LI.reg(), nullptr)) {
LI.markNotSpillable();
return -1.0f;
}
diff --git a/llvm/lib/CodeGen/CodeGenCommonISel.cpp b/llvm/lib/CodeGen/CodeGenCommonISel.cpp
index 577c5dbc8e2da8..fc56bbe5c5d020 100644
--- a/llvm/lib/CodeGen/CodeGenCommonISel.cpp
+++ b/llvm/lib/CodeGen/CodeGenCommonISel.cpp
@@ -260,7 +260,7 @@ void llvm::salvageDebugInfoForDbgValue(const MachineRegisterInfo &MRI,
continue;
}
- int UseMOIdx = DbgMI->findRegisterUseOperandIdx(DefMO->getReg());
+ int UseMOIdx = DbgMI->findRegisterUseOperandIdx(DefMO->getReg(), nullptr);
assert(UseMOIdx != -1 && DbgMI->hasDebugOperandForReg(DefMO->getReg()) &&
"Must use salvaged instruction as its location");
diff --git a/llvm/lib/CodeGen/EarlyIfConversion.cpp b/llvm/lib/CodeGen/EarlyIfConversion.cpp
index 31e107ade1ccbb..1eecf9e2a54e17 100644
--- a/llvm/lib/CodeGen/EarlyIfConversion.cpp
+++ b/llvm/lib/CodeGen/EarlyIfConversion.cpp
@@ -599,8 +599,8 @@ static bool hasSameValue(const MachineRegisterInfo &MRI,
return false;
// Further, check that the two defs come from corresponding operands.
- int TIdx = TDef->findRegisterDefOperandIdx(TReg);
- int FIdx = FDef->findRegisterDefOperandIdx(FReg);
+ int TIdx = TDef->findRegisterDefOperandIdx(TReg, nullptr);
+ int FIdx = FDef->findRegisterDefOperandIdx(FReg, nullptr);
if (TIdx == -1 || FIdx == -1)
return false;
diff --git a/llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp b/llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp
index 4d668c53f7156b..3bb9da5f1a37bb 100644
--- a/llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp
+++ b/llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp
@@ -112,7 +112,7 @@ static Register performCopyPropagation(Register Reg,
bool &IsKill, const TargetInstrInfo &TII,
const TargetRegisterInfo &TRI) {
// First check if statepoint itself uses Reg in non-meta operands.
- int Idx = RI->findRegisterUseOperandIdx(Reg, false, &TRI);
+ int Idx = RI->findRegisterUseOperandIdx(Reg, &TRI, false);
if (Idx >= 0 && (unsigned)Idx < StatepointOpers(&*RI).getNumDeoptArgsIdx()) {
IsKill = false;
return Reg;
diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
index d3f86af1e2908e..39eb5c42466ee2 100644
--- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
@@ -2749,8 +2749,8 @@ bool CombinerHelper::matchEqualDefs(const MachineOperand &MOP1,
// %5:_(s8), %6:_(s8), %7:_(s8), %8:_(s8) = G_UNMERGE_VALUES %4:_(<4 x s8>)
// I1 and I2 are different instructions but produce same values,
// %1 and %6 are same, %1 and %7 are not the same value.
- return I1->findRegisterDefOperandIdx(InstAndDef1->Reg) ==
- I2->findRegisterDefOperandIdx(InstAndDef2->Reg);
+ return I1->findRegisterDefOperandIdx(InstAndDef1->Reg, nullptr) ==
+ I2->findRegisterDefOperandIdx(InstAndDef2->Reg, nullptr);
}
return false;
}
diff --git a/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp b/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp
index bb5363fb2527b5..a0967746397f47 100644
--- a/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp
@@ -420,7 +420,8 @@ void RegBankSelect::tryAvoidingSplit(
// If the next terminator uses Reg, this means we have
// to split right after MI and thus we need a way to ask
// which outgoing edges are affected.
- assert(!Next->readsRegister(Reg) && "Need to split between terminators");
+ assert(!Next->readsRegister(Reg, nullptr) &&
+ "Need to split between terminators");
// We will split all the edges and repair there.
} else {
// This is a virtual register defined by a terminator.
diff --git a/llvm/lib/CodeGen/InlineSpiller.cpp b/llvm/lib/CodeGen/InlineSpiller.cpp
index c46b1fe18ca743..01e0adf03dcd1b 100644
--- a/llvm/lib/CodeGen/InlineSpiller.cpp
+++ b/llvm/lib/CodeGen/InlineSpiller.cpp
@@ -869,7 +869,7 @@ static void dumpMachineInstrRangeWithSlotIndex(MachineBasicBlock::iterator B,
// destination that is marked as an early clobber, print the
// early-clobber slot index.
if (VReg) {
- MachineOperand *MO = I->findRegisterDefOperand(VReg);
+ MachineOperand *MO = I->findRegisterDefOperand(VReg, nullptr);
if (MO && MO->isEarlyClobber())
Idx = Idx.getRegSlot(true);
}
diff --git a/llvm/lib/CodeGen/LiveVariables.cpp b/llvm/lib/CodeGen/LiveVariables.cpp
index b85526cfb380b6..10df5fe1aa96c8 100644
--- a/llvm/lib/CodeGen/LiveVariables.cpp
+++ b/llvm/lib/CodeGen/LiveVariables.cpp
@@ -258,7 +258,7 @@ void LiveVariables::HandlePhysRegUse(Register Reg, MachineInstr &MI) {
}
}
} else if (LastDef && !PhysRegUse[Reg] &&
- !LastDef->findRegisterDefOperand(Reg))
+ !LastDef->findRegisterDefOperand(Reg, nullptr))
// Last def defines the super register, add an implicit def of reg.
LastDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/,
true/*IsImp*/));
@@ -361,7 +361,8 @@ bool LiveVariables::HandlePhysRegKill(Register Reg, MachineInstr *MI) {
continue;
bool NeedDef = true;
if (PhysRegDef[Reg] == PhysRegDef[SubReg]) {
- MachineOperand *MO = PhysRegDef[Reg]->findRegisterDefOperand(SubReg);
+ MachineOperand *MO =
+ PhysRegDef[Reg]->findRegisterDefOperand(SubReg, nullptr);
if (MO) {
NeedDef = false;
assert(!MO->isDead());
@@ -388,7 +389,7 @@ bool LiveVariables::HandlePhysRegKill(Register Reg, MachineInstr *MI) {
true/*IsImp*/, true/*IsKill*/));
else {
MachineOperand *MO =
- LastRefOrPartRef->findRegisterDefOperand(Reg, false, false, TRI);
+ LastRefOrPartRef->findRegisterDefOperand(Reg, TRI, false, false);
bool NeedEC = MO->isEarlyClobber() && MO->getReg() != Reg;
// If the last reference is the last def, then it's not used at all.
// That is, unless we are currently processing the last reference itself.
@@ -396,7 +397,7 @@ bool LiveVariables::HandlePhysRegKill(Register Reg, MachineInstr *MI) {
if (NeedEC) {
// If we are adding a subreg def and the superreg def is marked early
// clobber, add an early clobber marker to the subreg def.
- MO = LastRefOrPartRef->findRegisterDefOperand(Reg);
+ MO = LastRefOrPartRef->findRegisterDefOperand(Reg, nullptr);
if (MO)
MO->setIsEarlyClobber();
}
@@ -727,7 +728,7 @@ void LiveVariables::recomputeForSingleDefVirtReg(Register Reg) {
if (MI.isPHI())
break;
if (MI.readsVirtualRegister(Reg)) {
- assert(!MI.killsRegister(Reg));
+ assert(!MI.killsRegister(Reg, nullptr));
MI.addRegisterKilled(Reg, nullptr);
VI.Kills.push_back(&MI);
break;
diff --git a/llvm/lib/CodeGen/MachineCSE.cpp b/llvm/lib/CodeGen/MachineCSE.cpp
index 26a8d00e662651..42cdcaa5bbf4f2 100644
--- a/llvm/lib/CodeGen/MachineCSE.cpp
+++ b/llvm/lib/CodeGen/MachineCSE.cpp
@@ -709,7 +709,7 @@ bool MachineCSE::ProcessBlockCSE(MachineBasicBlock *MBB) {
for (MachineBasicBlock::iterator II = CSMI, IE = &MI; II != IE; ++II)
for (auto ImplicitDef : ImplicitDefs)
if (MachineOperand *MO = II->findRegisterUseOperand(
- ImplicitDef, /*isKill=*/true, TRI))
+ ImplicitDef, TRI, /*isKill=*/true))
MO->setIsKill(false);
} else {
// If the instructions aren't in the same BB, bail out and clear the
diff --git a/llvm/lib/CodeGen/MachineCombiner.cpp b/llvm/lib/CodeGen/MachineCombiner.cpp
index a4c87a7678bd8d..3a50a17a0ebcfa 100644
--- a/llvm/lib/CodeGen/MachineCombiner.cpp
+++ b/llvm/lib/CodeGen/MachineCombiner.cpp
@@ -229,8 +229,8 @@ MachineCombiner::getDepth(SmallVectorImpl<MachineInstr *> &InsInstrs,
assert(DefInstr &&
"There must be a definition for a new virtual register");
DepthOp = InstrDepth[II->second];
- int DefIdx = DefInstr->findRegisterDefOperandIdx(MO.getReg());
- int UseIdx = InstrPtr->findRegisterUseOperandIdx(MO.getReg());
+ int DefIdx = DefInstr->findRegisterDefOperandIdx(MO.getReg(), nullptr);
+ int UseIdx = InstrPtr->findRegisterUseOperandIdx(MO.getReg(), nullptr);
LatencyOp = TSchedModel.computeOperandLatency(DefInstr, DefIdx,
InstrPtr, UseIdx);
} else {
@@ -241,8 +241,10 @@ MachineCombiner::getDepth(SmallVectorImpl<MachineInstr *> &InsInstrs,
DepthOp = BlockTrace.getInstrCycles(*DefInstr).Depth;
if (!isTransientMI(DefInstr))
LatencyOp = TSchedModel.computeOperandLatency(
- DefInstr, DefInstr->findRegisterDefOperandIdx(MO.getReg()),
- InstrPtr, InstrPtr->findRegisterUseOperandIdx(MO.getReg()));
+ DefInstr,
+ DefInstr->findRegisterDefOperandIdx(MO.getReg(), nullptr),
+ InstrPtr,
+ InstrPtr->findRegisterUseOperandIdx(MO.getReg(), nullptr));
}
}
IDepth = std::max(IDepth, DepthOp + LatencyOp);
@@ -280,8 +282,8 @@ unsigned MachineCombiner::getLatency(MachineInstr *Root, MachineInstr *NewRoot,
unsigned LatencyOp = 0;
if (UseMO && BlockTrace.isDepInTrace(*Root, *UseMO)) {
LatencyOp = TSchedModel.computeOperandLatency(
- NewRoot, NewRoot->findRegisterDefOperandIdx(MO.getReg()), UseMO,
- UseMO->findRegisterUseOperandIdx(MO.getReg()));
+ NewRoot, NewRoot->findRegisterDefOperandIdx(MO.getReg(), nullptr),
+ UseMO, UseMO->findRegisterUseOperandIdx(MO.getReg(), nullptr));
} else {
LatencyOp = TSchedModel.computeInstrLatency(NewRoot);
}
diff --git a/llvm/lib/CodeGen/MachineCopyPropagation.cpp b/llvm/lib/CodeGen/MachineCopyPropagation.cpp
index 9a0ab300b21b7a..30eea0d09ef628 100644
--- a/llvm/lib/CodeGen/MachineCopyPropagation.cpp
+++ b/llvm/lib/CodeGen/MachineCopyPropagation.cpp
@@ -720,7 +720,7 @@ void MachineCopyPropagation::forwardUses(MachineInstr &MI) {
// cannot cope with that.
if (isCopyInstr(MI, *TII, UseCopyInstr) &&
MI.modifiesRegister(Copy...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/85968
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