[llvm] [LLVM][AArch64]Use load/store with consecutive registers in SME2 or S… (PR #77665)

[Sander de Smalen via llvm-commits]

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@@ -2859,7 +2863,11 @@ static void computeCalleeSaveRegisterPairs(
           RPI.Reg2 = NextReg;
         break;
       case RegPairInfo::PPR:
+        break;
       case RegPairInfo::ZPR:
+        if (Subtarget.hasSVE2p1() || Subtarget.hasSME2())
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sdesmalen-arm wrote:

Is it worth creating a function like `bool useMultiVectorLoadStoreInPrologueEpilogue(Register R1, Register R2)` that returns true if the subtarget has SVE2p1 or SME2, and R1 and R2 are consecutive registers in the ZPRRegClass?

https://github.com/llvm/llvm-project/pull/77665