[llvm] [X86, CodeGen] Add a pattern in PreprocessISelDAG. (PR #85848)

[Peter Rong via llvm-commits]

DataCorrupted wrote:

> Why not do this in generic DAGCombine?
> 
> Or in getNode. I think we already special case i1 vectors for some operations.
> 
> Or make shifts of vXi1 vectors Expand which will cause them to scalarize.

I didn't want to deal with (potential) side effects on other arch, they can be messy if many tests changed :(
But now that @RKSimon is on it, we should have things fixed in generic DAGCombine soon.

https://github.com/llvm/llvm-project/pull/85848