[llvm] [SelectionDAG] Add MaskedValueIsZero check to allow folding of zero extended variables we know are safe to extend (PR #85573)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 19 11:16:52 PDT 2024
github-actions[bot] wrote:
<!--LLVM CODE FORMAT COMMENT: {clang-format}-->
:warning: C/C++ code formatter, clang-format found issues in your code. :warning:
<details>
<summary>
You can test this locally with the following command:
</summary>
``````````bash
git-clang-format --diff ef395a492aa931f428e99e1c0a93d4ad2fb0fcfa 86e897003bcc9b4dad6f9284b61110f65fd8142d -- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
``````````
</details>
<details>
<summary>
View the diff from clang-format here.
</summary>
``````````diff
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 8ab60b77c0..4957550a21 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -13850,9 +13850,9 @@ SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
// If the shift is too large, then see if we can deduce that the
// shift is safe anyway.
// Create a mask that has ones for the bits being shifted out.
- APInt ShiftOutMask = APInt::getHighBitsSet(
- ShVal.getValueSizeInBits(),
- ShAmtC->getAPIntValue().getZExtValue());
+ APInt ShiftOutMask =
+ APInt::getHighBitsSet(ShVal.getValueSizeInBits(),
+ ShAmtC->getAPIntValue().getZExtValue());
// Check if the bits being shifted out are known to be zero.
if (!DAG.MaskedValueIsZero(ShVal, ShiftOutMask))
``````````
</details>
https://github.com/llvm/llvm-project/pull/85573
More information about the llvm-commits
mailing list