[llvm] add ucmp and scmp support to SelectionDAG (PR #85822)

[Miguel Raz Guzmán Macedo via llvm-commits]

https://github.com/miguelraz created https://github.com/llvm/llvm-project/pull/85822

This PR is the next step after https://github.com/llvm/llvm-project/pull/83227 in a possible GSoC project to add 3 way comparison intrinsics to LLVM IR.

Steps as outline in the [documentation](https://llvm.org/docs/ExtendingLLVM.html#adding-a-new-selectiondag-node)
1. [X] Add an enum value for the SelectionDAG node in `.../ISDOpcodes.h`
2. [ ]  `CodeGen/SelectionDAG/SelectionDAG.cpp` - add code to print the node to `getOperationName`
3. [ ] `.../SelectionDAG/LegalizeDAG.cpp` - add legalize, promote, expand directives as necessary
4. [ ] ibid - size promotion of only applicable to same sizes
5. [ ] ibid - add a case for node in `ExpandOp` to teach legalizer for 64bits in 32bit targets
6. [ ] `SDAG/DAGCombiner.cpp` - add a visit function (see `visitFABS` and `visitSRL` as starting places
7. [ ] `llvm/Target/PowerPC/PPCISelLowering.cpp` - add native support if not default
8. [ ] `Target/TargetSelectionDAG.td` - add a `def` to that node with appropriate type constrains (see `add/bswap/fadd`)
9. [ ] `lib/Target/PowerPC/PPCInstrInfo.td` - add a pattern for new node that uses one or more target nodes (see `rotl` in `PPCInstrInfo.td`)
10. [ ] add complex patterns?
11. [ ] `test/CodeGen/*` add unit tests as you go

cc @nikic and @dc03-work 

>From b1c548cc51b2b5d6e31f196167005d75ef128f41 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Miguel=20Raz=20Guzm=C3=A1n=20Macedo?=
 <miguelraz at ciencias.unam.mx>
Date: Tue, 19 Mar 2024 10:46:15 -0600
Subject: [PATCH] add ucmp and scmp support to SelectionDAG

---
 llvm/include/llvm/CodeGen/ISDOpcodes.h         | 5 +++++
 llvm/include/llvm/CodeGen/TargetLowering.h     | 4 ++++
 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 6 ++++++
 llvm/unittests/Analysis/ValueTrackingTest.cpp  | 2 ++
 4 files changed, 17 insertions(+)

diff --git a/llvm/include/llvm/CodeGen/ISDOpcodes.h b/llvm/include/llvm/CodeGen/ISDOpcodes.h
index 49d51a27e3c0f6..287919fca14905 100644
--- a/llvm/include/llvm/CodeGen/ISDOpcodes.h
+++ b/llvm/include/llvm/CodeGen/ISDOpcodes.h
@@ -676,6 +676,11 @@ enum NodeType {
   UMIN,
   UMAX,
 
+  /// [US]CMP - Three way integer comparison - returns -1, 0, or 1 if
+  /// Op1 < Op2, Op1 == Op2, Op1 > Op2, respectively.
+  SCMP,
+  UCMP,
+
   /// Bitwise operators - logical and, logical or, logical xor.
   AND,
   OR,
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index 2f164a460db843..0786fc798f5748 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -5314,6 +5314,10 @@ class TargetLowering : public TargetLoweringBase {
   /// method accepts integers as its arguments.
   SDValue expandIntMINMAX(SDNode *Node, SelectionDAG &DAG) const;
 
+  /// Method for building the DAG expansion of ISD::[US]CMP. This
+  /// method accepts integers as its arguments.
+  SDValue expandCMP(SDNode *Node, SelectionDAG &DAG) const;
+
   /// Method for building the DAG expansion of ISD::[US][ADD|SUB]SAT. This
   /// method accepts integers as its arguments.
   SDValue expandAddSubSat(SDNode *Node, SelectionDAG &DAG) const;
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 6f6ed4bd45027b..e12a451bd105e7 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -6704,6 +6704,12 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
         VT.getVectorElementType() == MVT::i1)
       return getNode(ISD::XOR, DL, VT, N1, N2);
     break;
+  case ISD::UCMP:
+  case ISD::SCMP:
+    assert(VT.isInteger() && "This operator does not apply to FP types!");
+    assert(N1.getValueType() == N2.getValueType() && 
+           N1.getValueType() == VT && "Binary operator types must match");
+      break;
   case ISD::MUL:
     assert(VT.isInteger() && "This operator does not apply to FP types!");
     assert(N1.getValueType() == N2.getValueType() &&
diff --git a/llvm/unittests/Analysis/ValueTrackingTest.cpp b/llvm/unittests/Analysis/ValueTrackingTest.cpp
index 6c6897d83a256e..e78cbb4cc2644b 100644
--- a/llvm/unittests/Analysis/ValueTrackingTest.cpp
+++ b/llvm/unittests/Analysis/ValueTrackingTest.cpp
@@ -891,6 +891,8 @@ TEST(ValueTracking, propagatesPoison) {
       {true, "call i32 @llvm.smin.i32(i32 %x, i32 %y)", 0},
       {true, "call i32 @llvm.umax.i32(i32 %x, i32 %y)", 0},
       {true, "call i32 @llvm.umin.i32(i32 %x, i32 %y)", 0},
+      {true, "call i32 @llvm.scmp.i32.i32(i32 %x, i32 %y)", 0},
+      {true, "call i32 @llvm.ucmp.i32.i32(i32 %x, i32 %y)", 0},
       {true, "call i32 @llvm.bitreverse.i32(i32 %x)", 0},
       {true, "call i32 @llvm.bswap.i32(i32 %x)", 0},
       {false, "call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 %shamt)", 0},