[llvm] [RISCV] Add macro fusions for Xiangshan (PR #72362)

[Yinan Xu via llvm-commits]

poemonsense wrote:

> I added some MIR tests, but I think I need more data about performance. cc @dtcxzyw @poemonsense And, we may not need to support some fusions in LLVM since the patterns don't match what LLVM generates.

I'm glad to provide help for testing on RTL-simulation and real chips. We've already got the SoC board back.

https://github.com/llvm/llvm-project/pull/72362