[llvm] d1c3795 - Revert "Fix overflow flag for i128 USUBO"
Ulrich Weigand via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 19 03:43:17 PDT 2024
Author: Ulrich Weigand
Date: 2024-03-19T11:43:05+01:00
New Revision: d1c37959686db3303f6d5ffaeee12be12facc640
URL: https://github.com/llvm/llvm-project/commit/d1c37959686db3303f6d5ffaeee12be12facc640
DIFF: https://github.com/llvm/llvm-project/commit/d1c37959686db3303f6d5ffaeee12be12facc640.diff
LOG: Revert "Fix overflow flag for i128 USUBO"
This reverts commit d9c31ee9568277e4303715736b40925e41503596.
Added:
Modified:
llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
llvm/test/CodeGen/SystemZ/int-usub-12.ll
llvm/test/CodeGen/SystemZ/int-usub-13.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
index 6158b044e5db00..887c35a7ba240a 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -4263,7 +4263,6 @@ SDValue SystemZTargetLowering::lowerXALUO(SDValue Op,
if (N->getValueType(0) == MVT::i128) {
unsigned BaseOp = 0;
unsigned FlagOp = 0;
- bool IsBorrow = false;
switch (Op.getOpcode()) {
default: llvm_unreachable("Unknown instruction!");
case ISD::UADDO:
@@ -4273,7 +4272,6 @@ SDValue SystemZTargetLowering::lowerXALUO(SDValue Op,
case ISD::USUBO:
BaseOp = ISD::SUB;
FlagOp = SystemZISD::VSCBI;
- IsBorrow = true;
break;
}
SDValue Result = DAG.getNode(BaseOp, DL, MVT::i128, LHS, RHS);
@@ -4281,9 +4279,6 @@ SDValue SystemZTargetLowering::lowerXALUO(SDValue Op,
Flag = DAG.getNode(ISD::AssertZext, DL, MVT::i128, Flag,
DAG.getValueType(MVT::i1));
Flag = DAG.getZExtOrTrunc(Flag, DL, N->getValueType(1));
- if (IsBorrow)
- Flag = DAG.getNode(ISD::XOR, DL, Flag.getValueType(),
- Flag, DAG.getConstant(1, DL, Flag.getValueType()));
return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Result, Flag);
}
@@ -4356,7 +4351,6 @@ SDValue SystemZTargetLowering::lowerUADDSUBO_CARRY(SDValue Op,
if (VT == MVT::i128) {
unsigned BaseOp = 0;
unsigned FlagOp = 0;
- bool IsBorrow = false;
switch (Op.getOpcode()) {
default: llvm_unreachable("Unknown instruction!");
case ISD::UADDO_CARRY:
@@ -4366,21 +4360,14 @@ SDValue SystemZTargetLowering::lowerUADDSUBO_CARRY(SDValue Op,
case ISD::USUBO_CARRY:
BaseOp = SystemZISD::VSBI;
FlagOp = SystemZISD::VSBCBI;
- IsBorrow = true;
break;
}
- if (IsBorrow)
- Carry = DAG.getNode(ISD::XOR, DL, Carry.getValueType(),
- Carry, DAG.getConstant(1, DL, Carry.getValueType()));
Carry = DAG.getZExtOrTrunc(Carry, DL, MVT::i128);
SDValue Result = DAG.getNode(BaseOp, DL, MVT::i128, LHS, RHS, Carry);
SDValue Flag = DAG.getNode(FlagOp, DL, MVT::i128, LHS, RHS, Carry);
Flag = DAG.getNode(ISD::AssertZext, DL, MVT::i128, Flag,
DAG.getValueType(MVT::i1));
Flag = DAG.getZExtOrTrunc(Flag, DL, N->getValueType(1));
- if (IsBorrow)
- Flag = DAG.getNode(ISD::XOR, DL, Flag.getValueType(),
- Flag, DAG.getConstant(1, DL, Flag.getValueType()));
return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Result, Flag);
}
@@ -6584,27 +6571,6 @@ SDValue SystemZTargetLowering::combineTruncateExtract(
}
}
}
- // Convert (zext (xor (trunc X), C)) into (xor (trunc X), C') if the size
- // of the result is smaller than the size of X and all the truncated bits
- // of X are already zero.
- if (N0.getOpcode() == ISD::XOR &&
- N0.hasOneUse() && N0.getOperand(0).hasOneUse() &&
- N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
- N0.getOperand(1).getOpcode() == ISD::Constant) {
- SDValue X = N0.getOperand(0).getOperand(0);
- if (VT.isScalarInteger() && VT.getSizeInBits() < X.getValueSizeInBits()) {
- KnownBits Known = DAG.computeKnownBits(X);
- APInt TruncatedBits = APInt::getBitsSet(X.getValueSizeInBits(),
- N0.getValueSizeInBits(),
- VT.getSizeInBits());
- if (TruncatedBits.isSubsetOf(Known.Zero)) {
- X = DAG.getNode(ISD::TRUNCATE, SDLoc(X), VT, X);
- APInt Mask = N0.getConstantOperandAPInt(1).zext(VT.getSizeInBits());
- return DAG.getNode(ISD::XOR, SDLoc(N0), VT,
- X, DAG.getConstant(Mask, SDLoc(N0), VT));
- }
- }
- }
return SDValue();
}
diff --git a/llvm/test/CodeGen/SystemZ/int-usub-12.ll b/llvm/test/CodeGen/SystemZ/int-usub-12.ll
index 147fbfd920a9dc..c39a6da37048d3 100644
--- a/llvm/test/CodeGen/SystemZ/int-usub-12.ll
+++ b/llvm/test/CodeGen/SystemZ/int-usub-12.ll
@@ -11,7 +11,6 @@ define zeroext i1 @f1(i128 %a, i128 %b, ptr %res) {
; CHECK-NEXT: vscbiq %v2, %v1, %v0
; CHECK-NEXT: vlgvg %r2, %v2, 1
; CHECK-NEXT: vsq %v0, %v1, %v0
-; CHECK-NEXT: xilf %r2, 1
; CHECK-NEXT: vst %v0, 0(%r4), 3
; CHECK-NEXT: br %r14
%t = call {i128, i1} @llvm.usub.with.overflow.i128(i128 %a, i128 %b)
@@ -28,7 +27,6 @@ define zeroext i1 @f2(i128 %a, i128 %b) {
; CHECK-NEXT: vl %v1, 0(%r2), 3
; CHECK-NEXT: vscbiq %v0, %v1, %v0
; CHECK-NEXT: vlgvg %r2, %v0, 1
-; CHECK-NEXT: xilf %r2, 1
; CHECK-NEXT: br %r14
%t = call {i128, i1} @llvm.usub.with.overflow.i128(i128 %a, i128 %b)
%obit = extractvalue {i128, i1} %t, 1
@@ -48,25 +46,5 @@ define i128 @f3(i128 %a, i128 %b) {
ret i128 %val
}
-define i128 @f4(i128 %a, i128 %b) {
-; CHECK-LABEL: f4:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vl %v0, 0(%r4), 3
-; CHECK-NEXT: vl %v1, 0(%r3), 3
-; CHECK-NEXT: vscbiq %v2, %v1, %v0
-; CHECK-NEXT: vlgvf %r0, %v2, 3
-; CHECK-NEXT: vgbm %v2, 0
-; CHECK-NEXT: xilf %r0, 1
-; CHECK-NEXT: jl .LBB3_2
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: vsq %v2, %v1, %v0
-; CHECK-NEXT: .LBB3_2:
-; CHECK-NEXT: vst %v2, 0(%r2), 3
-; CHECK-NEXT: br %r14
- %val = call i128 @llvm.usub.sat.i128(i128 %a, i128 %b)
- ret i128 %val
-}
-
declare {i128, i1} @llvm.usub.with.overflow.i128(i128, i128) nounwind readnone
-declare i128 @llvm.usub.sat.i128(i128, i128) nounwind readnone
diff --git a/llvm/test/CodeGen/SystemZ/int-usub-13.ll b/llvm/test/CodeGen/SystemZ/int-usub-13.ll
index 794af3b73fbe2a..637e1a81de996f 100644
--- a/llvm/test/CodeGen/SystemZ/int-usub-13.ll
+++ b/llvm/test/CodeGen/SystemZ/int-usub-13.ll
@@ -15,7 +15,6 @@ define zeroext i1 @f1(i256 %a, i256 %b, ptr %res) {
; CHECK-NEXT: vlgvg %r2, %v5, 1
; CHECK-NEXT: vsbiq %v0, %v1, %v0, %v4
; CHECK-NEXT: vsq %v1, %v3, %v2
-; CHECK-NEXT: xilf %r2, 1
; CHECK-NEXT: vst %v1, 16(%r4), 3
; CHECK-NEXT: vst %v0, 0(%r4), 3
; CHECK-NEXT: br %r14
@@ -36,7 +35,6 @@ define zeroext i1 @f2(i256 %a, i256 %b) {
; CHECK-NEXT: vscbiq %v2, %v3, %v2
; CHECK-NEXT: vsbcbiq %v0, %v1, %v0, %v2
; CHECK-NEXT: vlgvg %r2, %v0, 1
-; CHECK-NEXT: xilf %r2, 1
; CHECK-NEXT: br %r14
%t = call {i256, i1} @llvm.usub.with.overflow.i256(i256 %a, i256 %b)
%obit = extractvalue {i256, i1} %t, 1
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