[llvm] [CodeGen][MISched] Add misched post-regalloc bidirectional scheduling (PR #77138)

[Wang Pengcheng via llvm-commits]

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@@ -51,3 +61,6 @@ body:             |
 # BOTTOMUP-NEXT: SU(1):   renamable $x13 = ADD renamable $x11, renamable $x10
 # BOTTOMUP-NEXT: SU(0):   renamable $x12 = MUL renamable $x11, renamable $x10
 # BOTTOMUP-NEXT: SU(2):   renamable $x14 = DIVW renamable $x12, renamable $x13
+
+# BIDIRECTIONAL: *** Final schedule for %bb.0 ***
+# BIDIRECTIONAL-NEXT: * Schedule table (Bidirectional): not implemented
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wangpc-pp wrote:

Maybe we can test SU nodes here, just like `llvm/test/CodeGen/AArch64/dump-schedule-trace.mir`.

https://github.com/llvm/llvm-project/pull/77138