[llvm] [RISCV][GISEL] Legalization, register bank selection, and instruction selection for scalable G_SELECT (PR #85540)

[Craig Topper via llvm-commits]

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@@ -401,6 +402,16 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
   case TargetOpcode::G_SELECT: {
     LLT Ty = MRI.getType(MI.getOperand(0).getReg());
 
+    if (Ty.isVector()) {
+      GSelect *Sel = cast<GSelect>(&MI);
+      LLT TestTy = MRI.getType(Sel->getCondReg());
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topperc wrote:

assert that TestTy is vector

https://github.com/llvm/llvm-project/pull/85540