[llvm] [SelectionDAG] Add MaskedValueIsZero check to allow folding of zero extended variables we know are safe to extend (PR #85573)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 18 08:51:39 PDT 2024
================
@@ -322,5 +322,46 @@ define void @g(i32 %a) nounwind {
ret void
}
+define i32 @shift_zext_shl(i8 zeroext %x) {
+; X86-LABEL: shift_zext_shl:
+; X86: # %bb.0:
+; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: andl $64, %eax
+; X86-NEXT: shll $9, %eax
+; X86-NEXT: retl
+;
+; X64-LABEL: shift_zext_shl:
+; X64: # %bb.0:
+; X64-NEXT: movl %edi, %eax
+; X64-NEXT: andl $64, %eax
+; X64-NEXT: shll $9, %eax
+; X64-NEXT: retq
+ %1 = and i8 %x, 64
+ %2 = zext i8 %1 to i16
+ %3 = shl i16 %2, 9
+ %4 = zext i16 %3 to i32
+ ret i32 %4
+}
+
+define i32 @shift_zext_shl2(i8 zeroext %x) {
+; X86-LABEL: shift_zext_shl2:
+; X86: # %bb.0:
+; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: andl $64, %eax
+; X86-NEXT: shll $9, %eax
+; X86-NEXT: retl
+;
+; X64-LABEL: shift_zext_shl2:
+; X64: # %bb.0:
+; X64-NEXT: movl %edi, %eax
+; X64-NEXT: andl $64, %eax
+; X64-NEXT: shll $9, %eax
+; X64-NEXT: retq
+ %1 = and i8 %x, 64
+ %2 = zext i8 %1 to i32
+ %3 = shl i32 %2, 9
+ ret i32 %3
+}
+
----------------
AtariDreams wrote:
// Try to mask before the extension to avoid having to generate a larger mask,
// possibly over several sub-vectors.
if (SrcVT.bitsLT(VT) && VT.isVector()) {
if (!LegalOperations || (TLI.isOperationLegal(ISD::AND, SrcVT) &&
TLI.isOperationLegal(ISD::ZERO_EXTEND, VT))) {
SDValue Op = N0.getOperand(0);
Op = DAG.getZeroExtendInReg(Op, DL, MinVT);
AddToWorklist(Op.getNode());
SDValue ZExtOrTrunc = DAG.getZExtOrTrunc(Op, DL, VT);
// Transfer the debug info; the new node is equivalent to N0.
DAG.transferDbgValues(N0, ZExtOrTrunc);
return ZExtOrTrunc;
}
}
Happens before the code in question, so this does not apply.
https://github.com/llvm/llvm-project/pull/85573
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