[llvm] c5177f1 - Silence potential overflow warning (#83272)

[via llvm-commits]

Author: Martin Wehking
Date: 2024-03-18T14:38:27Z
New Revision: c5177f149b43dcc5a39c2c1aefaf1bba8518fd2e

URL: https://github.com/llvm/llvm-project/commit/c5177f149b43dcc5a39c2c1aefaf1bba8518fd2e
DIFF: https://github.com/llvm/llvm-project/commit/c5177f149b43dcc5a39c2c1aefaf1bba8518fd2e.diff

LOG: Silence potential overflow warning (#83272)

Cast Offset variable to int64_t type directly inside a multiplication
and function call to utilize 64-bit arithmetic.

Ensure that the multiplication will not overflow.

A static analyzer warned about this since the function expects a 64-bit
argument, but the multiplication is evaluated inside a 32-bit context.

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index 5cd10aa0c3a707..79a7d1cf66c4d3 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -1753,12 +1753,12 @@ void SIRegisterInfo::buildVGPRSpillLoadStore(SGPRSpillBuilder &SB, int Index,
     unsigned Opc = ST.enableFlatScratch() ? AMDGPU::SCRATCH_LOAD_DWORD_SADDR
                                           : AMDGPU::BUFFER_LOAD_DWORD_OFFSET;
     buildSpillLoadStore(*SB.MBB, SB.MI, SB.DL, Opc, Index, SB.TmpVGPR, false,
-                        FrameReg, Offset * SB.EltSize, MMO, SB.RS);
+                        FrameReg, (int64_t)Offset * SB.EltSize, MMO, SB.RS);
   } else {
     unsigned Opc = ST.enableFlatScratch() ? AMDGPU::SCRATCH_STORE_DWORD_SADDR
                                           : AMDGPU::BUFFER_STORE_DWORD_OFFSET;
     buildSpillLoadStore(*SB.MBB, SB.MI, SB.DL, Opc, Index, SB.TmpVGPR, IsKill,
-                        FrameReg, Offset * SB.EltSize, MMO, SB.RS);
+                        FrameReg, (int64_t)Offset * SB.EltSize, MMO, SB.RS);
     // This only ever adds one VGPR spill
     SB.MFI.addToSpilledVGPRs(1);
   }