[llvm] Add MaskedValueIsZero check (PR #85573)

[via llvm-commits]

https://github.com/AtariDreams updated https://github.com/llvm/llvm-project/pull/85573

>From f50fe3de14b8fc0dbaa8ff1b54cc295430e90301 Mon Sep 17 00:00:00 2001
From: Rose <gfunni234 at gmail.com>
Date: Sun, 17 Mar 2024 12:51:41 -0400
Subject: [PATCH] Add MaskedValueIsZero check

Add ones for every high bit that will cleared.

We can remove the ugt check because if the masked value is zero, then ugt will always be true anyway.
---
 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index b6a5925123f13f..01d523273d5456 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -13802,11 +13802,16 @@ SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
         if (N0.getOpcode() == ISD::SHL) {
           // If the original shl may be shifting out bits, do not perform this
           // transformation.
-          // TODO: Add MaskedValueIsZero check.
-          unsigned KnownZeroBits = ShVal.getValueSizeInBits() -
-                                   ShVal.getOperand(0).getValueSizeInBits();
-          if (ShAmtC->getAPIntValue().ugt(KnownZeroBits))
+
+          // Create a mask that has ones for the bits being shifted out.
+          llvm::APInt ShiftOutMask = llvm::APInt::getHighBitsSet(
+              ShVal.getValueSizeInBits(),
+              ShAmtC->getAPIntValue().getZExtValue());
+
+          // Check if the bits being shifted out are known to be zero.
+          if (!DAG.MaskedValueIsZero(ShVal, ShiftOutMask)) {
             return SDValue();
+          }
         }
 
         // Ensure that the shift amount is wide enough for the shifted value.