[llvm] Add MaskedValueIsZero check (PR #85573)
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Sun Mar 17 09:52:43 PDT 2024
https://github.com/AtariDreams created https://github.com/llvm/llvm-project/pull/85573
None
>From 670d54c8b2f7a9510098fd5d2f949fda10a7339f Mon Sep 17 00:00:00 2001
From: Rose <gfunni234 at gmail.com>
Date: Sun, 17 Mar 2024 12:51:41 -0400
Subject: [PATCH] Add MaskedValueIsZero check
---
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 14 +++++++++++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index b6a5925123f13f..e733916eaeefdb 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -13802,11 +13802,19 @@ SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
if (N0.getOpcode() == ISD::SHL) {
// If the original shl may be shifting out bits, do not perform this
// transformation.
- // TODO: Add MaskedValueIsZero check.
unsigned KnownZeroBits = ShVal.getValueSizeInBits() -
ShVal.getOperand(0).getValueSizeInBits();
- if (ShAmtC->getAPIntValue().ugt(KnownZeroBits))
- return SDValue();
+ if (ShAmtC->getAPIntValue().ugt(KnownZeroBits)) {
+ // Create a mask that has ones for the bits being shifted out.
+ llvm::APInt ShiftOutMask = llvm::APInt::getHighBitsSet(
+ ShVal.getValueSizeInBits(),
+ ShAmtC->getAPIntValue().getZExtValue());
+
+ // Check if the bits being shifted out are known to be zero.
+ if (!DAG.MaskedValueIsZero(ShVal, ShiftOutMask)) {
+ return SDValue();
+ }
+ }
}
// Ensure that the shift amount is wide enough for the shifted value.
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