[llvm] [NFC][LLVM][SVE][ISel] Remove redundant type information from Pat targets. (PR #85409)
Paul Walker via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 15 10:07:32 PDT 2024
https://github.com/paulwalker-arm updated https://github.com/llvm/llvm-project/pull/85409
>From ce8dfe0d3331fc62ba94e24b08dee3469d007511 Mon Sep 17 00:00:00 2001
From: Paul Walker <paul.walker at arm.com>
Date: Fri, 8 Mar 2024 20:58:40 +0000
Subject: [PATCH 1/2] [NFC][LLVM][SVE][ISel] Remove redundant type information
from Pat targets.
---
.../lib/Target/AArch64/AArch64SVEInstrInfo.td | 128 +++++++++---------
llvm/lib/Target/AArch64/SVEInstrFormats.td | 44 +++---
2 files changed, 84 insertions(+), 88 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
index e0a010af415534..120982697a473d 100644
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -2042,9 +2042,8 @@ let Predicates = [HasSVEorSME] in {
defm CNTP_XPP : sve_int_pcount_pred<0b0000, "cntp", int_aarch64_sve_cntp>;
def : Pat<(i64 (AArch64CttzElts nxv16i1:$Op1)),
- (i64 (!cast<Instruction>(CNTP_XPP_B)
- (nxv16i1 (!cast<Instruction>(BRKB_PPzP) (PTRUE_B 31), nxv16i1:$Op1)),
- (nxv16i1 (!cast<Instruction>(BRKB_PPzP) (PTRUE_B 31), nxv16i1:$Op1))))>;
+ (CNTP_XPP_B (BRKB_PPzP (PTRUE_B 31), PPR:$Op1),
+ (BRKB_PPzP (PTRUE_B 31), PPR:$Op1))>;
}
defm INCB_XPiI : sve_int_pred_pattern_a<0b000, "incb", add, int_aarch64_sve_cntb>;
@@ -2131,15 +2130,12 @@ let Predicates = [HasSVEorSME] in {
defm DECP_ZP : sve_int_count_v<0b10100, "decp">;
def : Pat<(i64 (add GPR64:$Op1, (i64 (AArch64CttzElts nxv16i1:$Op2)))),
- (i64 (!cast<Instruction>(INCP_XP_B)
- (nxv16i1 (!cast<Instruction>(BRKB_PPzP) (PTRUE_B 31), nxv16i1:$Op2)),
- GPR64:$Op1))>;
+ (INCP_XP_B (BRKB_PPzP (PTRUE_B 31), PPR:$Op2), GPR64:$Op1)>;
def : Pat<(i32 (add GPR32:$Op1, (trunc (i64 (AArch64CttzElts nxv16i1:$Op2))))),
- (i32 (EXTRACT_SUBREG (i64 (!cast<Instruction>(INCP_XP_B)
- (nxv16i1 (!cast<Instruction>(BRKB_PPzP) (PTRUE_B 31), nxv16i1:$Op2)),
- (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Op1, sub_32))),
- sub_32))>;
+ (EXTRACT_SUBREG (INCP_XP_B (BRKB_PPzP (PTRUE_B 31), PPR:$Op2),
+ (INSERT_SUBREG (IMPLICIT_DEF), GPR32:$Op1, sub_32)),
+ sub_32)>;
defm INDEX_RR : sve_int_index_rr<"index", AArch64mul_p_oneuse>;
defm INDEX_IR : sve_int_index_ir<"index", AArch64mul_p, AArch64mul_p_oneuse>;
@@ -2521,9 +2517,9 @@ let Predicates = [HasSVEorSME] in {
(ADDVL_XXI GPR64:$op, $imm)>;
def : Pat<(add GPR32:$op, (i32 (trunc (vscale (sve_rdvl_imm i32:$imm))))),
- (i32 (EXTRACT_SUBREG (ADDVL_XXI (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
- GPR32:$op, sub_32), $imm),
- sub_32))>;
+ (EXTRACT_SUBREG (ADDVL_XXI (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
+ GPR32:$op, sub_32), $imm),
+ sub_32)>;
def : Pat<(add GPR64:$op, (vscale (sve_cnth_imm i32:$imm))),
(INCH_XPiI GPR64:$op, 31, $imm)>;
@@ -2540,30 +2536,30 @@ let Predicates = [HasSVEorSME] in {
(DECD_XPiI GPR64:$op, 31, $imm)>;
def : Pat<(add GPR32:$op, (i32 (trunc (vscale (sve_cnth_imm i32:$imm))))),
- (i32 (EXTRACT_SUBREG (INCH_XPiI (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
- GPR32:$op, sub_32), 31, $imm),
- sub_32))>;
+ (EXTRACT_SUBREG (INCH_XPiI (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
+ GPR32:$op, sub_32), 31, $imm),
+ sub_32)>;
def : Pat<(add GPR32:$op, (i32 (trunc (vscale (sve_cntw_imm i32:$imm))))),
- (i32 (EXTRACT_SUBREG (INCW_XPiI (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
- GPR32:$op, sub_32), 31, $imm),
- sub_32))>;
+ (EXTRACT_SUBREG (INCW_XPiI (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
+ GPR32:$op, sub_32), 31, $imm),
+ sub_32)>;
def : Pat<(add GPR32:$op, (i32 (trunc (vscale (sve_cntd_imm i32:$imm))))),
- (i32 (EXTRACT_SUBREG (INCD_XPiI (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
- GPR32:$op, sub_32), 31, $imm),
- sub_32))>;
+ (EXTRACT_SUBREG (INCD_XPiI (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
+ GPR32:$op, sub_32), 31, $imm),
+ sub_32)>;
def : Pat<(add GPR32:$op, (i32 (trunc (vscale (sve_cnth_imm_neg i32:$imm))))),
- (i32 (EXTRACT_SUBREG (DECH_XPiI (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
- GPR32:$op, sub_32), 31, $imm),
- sub_32))>;
+ (EXTRACT_SUBREG (DECH_XPiI (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
+ GPR32:$op, sub_32), 31, $imm),
+ sub_32)>;
def : Pat<(add GPR32:$op, (i32 (trunc (vscale (sve_cntw_imm_neg i32:$imm))))),
- (i32 (EXTRACT_SUBREG (DECW_XPiI (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
- GPR32:$op, sub_32), 31, $imm),
- sub_32))>;
+ (EXTRACT_SUBREG (DECW_XPiI (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
+ GPR32:$op, sub_32), 31, $imm),
+ sub_32)>;
def : Pat<(add GPR32:$op, (i32 (trunc (vscale (sve_cntd_imm_neg i32:$imm))))),
- (i32 (EXTRACT_SUBREG (DECD_XPiI (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
- GPR32:$op, sub_32), 31, $imm),
- sub_32))>;
+ (EXTRACT_SUBREG (DECD_XPiI (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
+ GPR32:$op, sub_32), 31, $imm),
+ sub_32)>;
}
// FIXME: BigEndian requires an additional REV instruction to satisfy the
@@ -3266,58 +3262,58 @@ let Predicates = [HasSVEorSME] in {
// Extract element from vector with immediate index that's within the bottom 128-bits.
let Predicates = [IsNeonAvailable], AddedComplexity = 1 in {
def : Pat<(i32 (vector_extract (nxv16i8 ZPR:$vec), VectorIndexB:$index)),
- (i32 (UMOVvi8 (v16i8 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexB:$index))>;
+ (UMOVvi8 (v16i8 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexB:$index)>;
def : Pat<(i32 (vector_extract (nxv8i16 ZPR:$vec), VectorIndexH:$index)),
- (i32 (UMOVvi16 (v8i16 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexH:$index))>;
+ (UMOVvi16 (v8i16 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexH:$index)>;
def : Pat<(i32 (vector_extract (nxv4i32 ZPR:$vec), VectorIndexS:$index)),
- (i32 (UMOVvi32 (v4i32 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexS:$index))>;
+ (UMOVvi32 (v4i32 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexS:$index)>;
def : Pat<(i64 (vector_extract (nxv2i64 ZPR:$vec), VectorIndexD:$index)),
- (i64 (UMOVvi64 (v2i64 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexD:$index))>;
+ (UMOVvi64 (v2i64 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexD:$index)>;
} // End IsNeonAvailable
let Predicates = [IsNeonAvailable] in {
def : Pat<(sext_inreg (vector_extract (nxv16i8 ZPR:$vec), VectorIndexB:$index), i8),
- (i32 (SMOVvi8to32 (v16i8 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexB:$index))>;
+ (SMOVvi8to32 (v16i8 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexB:$index)>;
def : Pat<(sext_inreg (anyext (i32 (vector_extract (nxv16i8 ZPR:$vec), VectorIndexB:$index))), i8),
- (i64 (SMOVvi8to64 (v16i8 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexB:$index))>;
+ (SMOVvi8to64 (v16i8 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexB:$index)>;
def : Pat<(sext_inreg (vector_extract (nxv8i16 ZPR:$vec), VectorIndexH:$index), i16),
- (i32 (SMOVvi16to32 (v8i16 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexH:$index))>;
+ (SMOVvi16to32 (v8i16 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexH:$index)>;
def : Pat<(sext_inreg (anyext (i32 (vector_extract (nxv8i16 ZPR:$vec), VectorIndexH:$index))), i16),
- (i64 (SMOVvi16to64 (v8i16 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexH:$index))>;
+ (SMOVvi16to64 (v8i16 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexH:$index)>;
def : Pat<(sext (i32 (vector_extract (nxv4i32 ZPR:$vec), VectorIndexS:$index))),
- (i64 (SMOVvi32to64 (v4i32 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexS:$index))>;
+ (SMOVvi32to64 (v4i32 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexS:$index)>;
} // End IsNeonAvailable
// Extract first element from vector.
let AddedComplexity = 2 in {
- def : Pat<(vector_extract (nxv16i8 ZPR:$Zs), (i64 0)),
- (i32 (EXTRACT_SUBREG ZPR:$Zs, ssub))>;
- def : Pat<(vector_extract (nxv8i16 ZPR:$Zs), (i64 0)),
- (i32 (EXTRACT_SUBREG ZPR:$Zs, ssub))>;
- def : Pat<(vector_extract (nxv4i32 ZPR:$Zs), (i64 0)),
- (i32 (EXTRACT_SUBREG ZPR:$Zs, ssub))>;
- def : Pat<(vector_extract (nxv2i64 ZPR:$Zs), (i64 0)),
- (i64 (EXTRACT_SUBREG ZPR:$Zs, dsub))>;
- def : Pat<(vector_extract (nxv8f16 ZPR:$Zs), (i64 0)),
- (f16 (EXTRACT_SUBREG ZPR:$Zs, hsub))>;
- def : Pat<(vector_extract (nxv4f16 ZPR:$Zs), (i64 0)),
- (f16 (EXTRACT_SUBREG ZPR:$Zs, hsub))>;
- def : Pat<(vector_extract (nxv2f16 ZPR:$Zs), (i64 0)),
- (f16 (EXTRACT_SUBREG ZPR:$Zs, hsub))>;
- def : Pat<(vector_extract (nxv8bf16 ZPR:$Zs), (i64 0)),
- (bf16 (EXTRACT_SUBREG ZPR:$Zs, hsub))>;
- def : Pat<(vector_extract (nxv4bf16 ZPR:$Zs), (i64 0)),
- (bf16 (EXTRACT_SUBREG ZPR:$Zs, hsub))>;
- def : Pat<(vector_extract (nxv2bf16 ZPR:$Zs), (i64 0)),
- (bf16 (EXTRACT_SUBREG ZPR:$Zs, hsub))>;
- def : Pat<(vector_extract (nxv4f32 ZPR:$Zs), (i64 0)),
- (f32 (EXTRACT_SUBREG ZPR:$Zs, ssub))>;
- def : Pat<(vector_extract (nxv2f32 ZPR:$Zs), (i64 0)),
- (f32 (EXTRACT_SUBREG ZPR:$Zs, ssub))>;
- def : Pat<(vector_extract (nxv2f64 ZPR:$Zs), (i64 0)),
- (f64 (EXTRACT_SUBREG ZPR:$Zs, dsub))>;
+ def : Pat<(i32 (vector_extract (nxv16i8 ZPR:$Zs), (i64 0))),
+ (EXTRACT_SUBREG ZPR:$Zs, ssub)>;
+ def : Pat<(i32 (vector_extract (nxv8i16 ZPR:$Zs), (i64 0))),
+ (EXTRACT_SUBREG ZPR:$Zs, ssub)>;
+ def : Pat<(i32 (vector_extract (nxv4i32 ZPR:$Zs), (i64 0))),
+ (EXTRACT_SUBREG ZPR:$Zs, ssub)>;
+ def : Pat<(i64 (vector_extract (nxv2i64 ZPR:$Zs), (i64 0))),
+ (EXTRACT_SUBREG ZPR:$Zs, dsub)>;
+ def : Pat<(f16 (vector_extract (nxv8f16 ZPR:$Zs), (i64 0))),
+ (EXTRACT_SUBREG ZPR:$Zs, hsub)>;
+ def : Pat<(f16 (vector_extract (nxv4f16 ZPR:$Zs), (i64 0))),
+ (EXTRACT_SUBREG ZPR:$Zs, hsub)>;
+ def : Pat<(f16 (vector_extract (nxv2f16 ZPR:$Zs), (i64 0))),
+ (EXTRACT_SUBREG ZPR:$Zs, hsub)>;
+ def : Pat<(bf16 (vector_extract (nxv8bf16 ZPR:$Zs), (i64 0))),
+ (EXTRACT_SUBREG ZPR:$Zs, hsub)>;
+ def : Pat<(bf16 (vector_extract (nxv4bf16 ZPR:$Zs), (i64 0))),
+ (EXTRACT_SUBREG ZPR:$Zs, hsub)>;
+ def : Pat<(bf16 (vector_extract (nxv2bf16 ZPR:$Zs), (i64 0))),
+ (EXTRACT_SUBREG ZPR:$Zs, hsub)>;
+ def : Pat<(f32 (vector_extract (nxv4f32 ZPR:$Zs), (i64 0))),
+ (EXTRACT_SUBREG ZPR:$Zs, ssub)>;
+ def : Pat<(f32 (vector_extract (nxv2f32 ZPR:$Zs), (i64 0))),
+ (EXTRACT_SUBREG ZPR:$Zs, ssub)>;
+ def : Pat<(f64 (vector_extract (nxv2f64 ZPR:$Zs), (i64 0))),
+ (EXTRACT_SUBREG ZPR:$Zs, dsub)>;
}
multiclass sve_predicated_add<SDNode extend, int value> {
diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td
index 826750222ab734..0a4025bf36f2dd 100644
--- a/llvm/lib/Target/AArch64/SVEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td
@@ -958,39 +958,39 @@ multiclass sve_int_count_r_x64<bits<5> opc, string asm,
// combine_op(x, trunc(cntp(all_active, p))) ==> inst p, x
def : Pat<(i32 (combine_op GPR32:$Rn, (trunc (int_aarch64_sve_cntp_oneuse (nxv16i1 (SVEAllActive)), (nxv16i1 PPRAny:$pred))))),
- (i32 (EXTRACT_SUBREG (!cast<Instruction>(NAME # _B) PPRAny:$pred,
+ (EXTRACT_SUBREG (!cast<Instruction>(NAME # _B) PPRAny:$pred,
(INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32)),
- sub_32))>;
+ sub_32)>;
def : Pat<(i32 (combine_op GPR32:$Rn, (trunc (int_aarch64_sve_cntp_oneuse (nxv8i1 (SVEAllActive)), (nxv8i1 PPRAny:$pred))))),
- (i32 (EXTRACT_SUBREG (!cast<Instruction>(NAME # _H) PPRAny:$pred,
+ (EXTRACT_SUBREG (!cast<Instruction>(NAME # _H) PPRAny:$pred,
(INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32)),
- sub_32))>;
+ sub_32)>;
def : Pat<(i32 (combine_op GPR32:$Rn, (trunc (int_aarch64_sve_cntp_oneuse (nxv4i1 (SVEAllActive)), (nxv4i1 PPRAny:$pred))))),
- (i32 (EXTRACT_SUBREG (!cast<Instruction>(NAME # _S) PPRAny:$pred,
+ (EXTRACT_SUBREG (!cast<Instruction>(NAME # _S) PPRAny:$pred,
(INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32)),
- sub_32))>;
+ sub_32)>;
def : Pat<(i32 (combine_op GPR32:$Rn, (trunc (int_aarch64_sve_cntp_oneuse (nxv2i1 (SVEAllActive)), (nxv2i1 PPRAny:$pred))))),
- (i32 (EXTRACT_SUBREG (!cast<Instruction>(NAME # _D) PPRAny:$pred,
+ (EXTRACT_SUBREG (!cast<Instruction>(NAME # _D) PPRAny:$pred,
(INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32)),
- sub_32))>;
+ sub_32)>;
// combine_op(x, trunc(cntp(p, p))) ==> inst p, x
def : Pat<(i32 (combine_op GPR32:$Rn, (trunc (int_aarch64_sve_cntp_oneuse (nxv16i1 PPRAny:$pred), (nxv16i1 PPRAny:$pred))))),
- (i32 (EXTRACT_SUBREG (!cast<Instruction>(NAME # _B) PPRAny:$pred,
+ (EXTRACT_SUBREG (!cast<Instruction>(NAME # _B) PPRAny:$pred,
(INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32)),
- sub_32))>;
+ sub_32)>;
def : Pat<(i32 (combine_op GPR32:$Rn, (trunc (int_aarch64_sve_cntp_oneuse (nxv8i1 PPRAny:$pred), (nxv8i1 PPRAny:$pred))))),
- (i32 (EXTRACT_SUBREG (!cast<Instruction>(NAME # _H) PPRAny:$pred,
+ (EXTRACT_SUBREG (!cast<Instruction>(NAME # _H) PPRAny:$pred,
(INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32)),
- sub_32))>;
+ sub_32)>;
def : Pat<(i32 (combine_op GPR32:$Rn, (trunc (int_aarch64_sve_cntp_oneuse (nxv4i1 PPRAny:$pred), (nxv4i1 PPRAny:$pred))))),
- (i32 (EXTRACT_SUBREG (!cast<Instruction>(NAME # _S) PPRAny:$pred,
+ (EXTRACT_SUBREG (!cast<Instruction>(NAME # _S) PPRAny:$pred,
(INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32)),
- sub_32))>;
+ sub_32)>;
def : Pat<(i32 (combine_op GPR32:$Rn, (trunc (int_aarch64_sve_cntp_oneuse (nxv2i1 PPRAny:$pred), (nxv2i1 PPRAny:$pred))))),
- (i32 (EXTRACT_SUBREG (!cast<Instruction>(NAME # _D) PPRAny:$pred,
+ (EXTRACT_SUBREG (!cast<Instruction>(NAME # _D) PPRAny:$pred,
(INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32)),
- sub_32))>;
+ sub_32)>;
}
class sve_int_count_v<bits<2> sz8_64, bits<5> opc, string asm,
@@ -1195,19 +1195,19 @@ multiclass sve_int_pred_pattern_a<bits<3> opc, string asm,
(!cast<Instruction>(NAME) GPR64:$Rdn, sve_pred_enum:$pattern, $imm)>;
def : Pat<(i32 (op GPR32:$Rdn, (i32 (trunc (opcnt (sve_pred_enum:$pattern)))))),
- (i32 (EXTRACT_SUBREG (!cast<Instruction>(NAME) (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
+ (EXTRACT_SUBREG (!cast<Instruction>(NAME) (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
GPR32:$Rdn, sub_32), sve_pred_enum:$pattern, 1),
- sub_32))>;
+ sub_32)>;
def : Pat<(i32 (op GPR32:$Rdn, (mul (i32 (trunc (opcnt (sve_pred_enum:$pattern)))), (sve_cnt_mul_imm_i32 i32:$imm)))),
- (i32 (EXTRACT_SUBREG (!cast<Instruction>(NAME) (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
+ (EXTRACT_SUBREG (!cast<Instruction>(NAME) (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
GPR32:$Rdn, sub_32), sve_pred_enum:$pattern, $imm),
- sub_32))>;
+ sub_32)>;
def : Pat<(i32 (op GPR32:$Rdn, (shl (i32 (trunc (opcnt (sve_pred_enum:$pattern)))), (sve_cnt_shl_imm i32:$imm)))),
- (i32 (EXTRACT_SUBREG (!cast<Instruction>(NAME) (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
+ (EXTRACT_SUBREG (!cast<Instruction>(NAME) (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
GPR32:$Rdn, sub_32), sve_pred_enum:$pattern, $imm),
- sub_32))>;
+ sub_32)>;
}
}
>From bbfa59778d58a5b013fa58ae7638f2a1c1004520 Mon Sep 17 00:00:00 2001
From: Paul Walker <paul.walker at arm.com>
Date: Fri, 15 Mar 2024 17:06:21 +0000
Subject: [PATCH 2/2] Convert more instances of (i64 (IMPLICIT_DEF)) to
(IMPLICIT_DEF).
---
.../lib/Target/AArch64/AArch64SVEInstrInfo.td | 14 ++++++------
llvm/lib/Target/AArch64/SVEInstrFormats.td | 22 +++++++++----------
2 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
index 120982697a473d..dd5e11c0f5e35d 100644
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -2517,7 +2517,7 @@ let Predicates = [HasSVEorSME] in {
(ADDVL_XXI GPR64:$op, $imm)>;
def : Pat<(add GPR32:$op, (i32 (trunc (vscale (sve_rdvl_imm i32:$imm))))),
- (EXTRACT_SUBREG (ADDVL_XXI (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
+ (EXTRACT_SUBREG (ADDVL_XXI (INSERT_SUBREG (IMPLICIT_DEF),
GPR32:$op, sub_32), $imm),
sub_32)>;
@@ -2536,28 +2536,28 @@ let Predicates = [HasSVEorSME] in {
(DECD_XPiI GPR64:$op, 31, $imm)>;
def : Pat<(add GPR32:$op, (i32 (trunc (vscale (sve_cnth_imm i32:$imm))))),
- (EXTRACT_SUBREG (INCH_XPiI (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
+ (EXTRACT_SUBREG (INCH_XPiI (INSERT_SUBREG (IMPLICIT_DEF),
GPR32:$op, sub_32), 31, $imm),
sub_32)>;
def : Pat<(add GPR32:$op, (i32 (trunc (vscale (sve_cntw_imm i32:$imm))))),
- (EXTRACT_SUBREG (INCW_XPiI (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
+ (EXTRACT_SUBREG (INCW_XPiI (INSERT_SUBREG (IMPLICIT_DEF),
GPR32:$op, sub_32), 31, $imm),
sub_32)>;
def : Pat<(add GPR32:$op, (i32 (trunc (vscale (sve_cntd_imm i32:$imm))))),
- (EXTRACT_SUBREG (INCD_XPiI (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
+ (EXTRACT_SUBREG (INCD_XPiI (INSERT_SUBREG (IMPLICIT_DEF),
GPR32:$op, sub_32), 31, $imm),
sub_32)>;
def : Pat<(add GPR32:$op, (i32 (trunc (vscale (sve_cnth_imm_neg i32:$imm))))),
- (EXTRACT_SUBREG (DECH_XPiI (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
+ (EXTRACT_SUBREG (DECH_XPiI (INSERT_SUBREG (IMPLICIT_DEF),
GPR32:$op, sub_32), 31, $imm),
sub_32)>;
def : Pat<(add GPR32:$op, (i32 (trunc (vscale (sve_cntw_imm_neg i32:$imm))))),
- (EXTRACT_SUBREG (DECW_XPiI (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
+ (EXTRACT_SUBREG (DECW_XPiI (INSERT_SUBREG (IMPLICIT_DEF),
GPR32:$op, sub_32), 31, $imm),
sub_32)>;
def : Pat<(add GPR32:$op, (i32 (trunc (vscale (sve_cntd_imm_neg i32:$imm))))),
- (EXTRACT_SUBREG (DECD_XPiI (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
+ (EXTRACT_SUBREG (DECD_XPiI (INSERT_SUBREG (IMPLICIT_DEF),
GPR32:$op, sub_32), 31, $imm),
sub_32)>;
}
diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td
index 0a4025bf36f2dd..1e76d58669da11 100644
--- a/llvm/lib/Target/AArch64/SVEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td
@@ -959,37 +959,37 @@ multiclass sve_int_count_r_x64<bits<5> opc, string asm,
// combine_op(x, trunc(cntp(all_active, p))) ==> inst p, x
def : Pat<(i32 (combine_op GPR32:$Rn, (trunc (int_aarch64_sve_cntp_oneuse (nxv16i1 (SVEAllActive)), (nxv16i1 PPRAny:$pred))))),
(EXTRACT_SUBREG (!cast<Instruction>(NAME # _B) PPRAny:$pred,
- (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32)),
+ (INSERT_SUBREG (IMPLICIT_DEF), GPR32:$Rn, sub_32)),
sub_32)>;
def : Pat<(i32 (combine_op GPR32:$Rn, (trunc (int_aarch64_sve_cntp_oneuse (nxv8i1 (SVEAllActive)), (nxv8i1 PPRAny:$pred))))),
(EXTRACT_SUBREG (!cast<Instruction>(NAME # _H) PPRAny:$pred,
- (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32)),
+ (INSERT_SUBREG (IMPLICIT_DEF), GPR32:$Rn, sub_32)),
sub_32)>;
def : Pat<(i32 (combine_op GPR32:$Rn, (trunc (int_aarch64_sve_cntp_oneuse (nxv4i1 (SVEAllActive)), (nxv4i1 PPRAny:$pred))))),
(EXTRACT_SUBREG (!cast<Instruction>(NAME # _S) PPRAny:$pred,
- (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32)),
+ (INSERT_SUBREG (IMPLICIT_DEF), GPR32:$Rn, sub_32)),
sub_32)>;
def : Pat<(i32 (combine_op GPR32:$Rn, (trunc (int_aarch64_sve_cntp_oneuse (nxv2i1 (SVEAllActive)), (nxv2i1 PPRAny:$pred))))),
(EXTRACT_SUBREG (!cast<Instruction>(NAME # _D) PPRAny:$pred,
- (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32)),
+ (INSERT_SUBREG (IMPLICIT_DEF), GPR32:$Rn, sub_32)),
sub_32)>;
// combine_op(x, trunc(cntp(p, p))) ==> inst p, x
def : Pat<(i32 (combine_op GPR32:$Rn, (trunc (int_aarch64_sve_cntp_oneuse (nxv16i1 PPRAny:$pred), (nxv16i1 PPRAny:$pred))))),
(EXTRACT_SUBREG (!cast<Instruction>(NAME # _B) PPRAny:$pred,
- (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32)),
+ (INSERT_SUBREG (IMPLICIT_DEF), GPR32:$Rn, sub_32)),
sub_32)>;
def : Pat<(i32 (combine_op GPR32:$Rn, (trunc (int_aarch64_sve_cntp_oneuse (nxv8i1 PPRAny:$pred), (nxv8i1 PPRAny:$pred))))),
(EXTRACT_SUBREG (!cast<Instruction>(NAME # _H) PPRAny:$pred,
- (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32)),
+ (INSERT_SUBREG (IMPLICIT_DEF), GPR32:$Rn, sub_32)),
sub_32)>;
def : Pat<(i32 (combine_op GPR32:$Rn, (trunc (int_aarch64_sve_cntp_oneuse (nxv4i1 PPRAny:$pred), (nxv4i1 PPRAny:$pred))))),
(EXTRACT_SUBREG (!cast<Instruction>(NAME # _S) PPRAny:$pred,
- (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32)),
+ (INSERT_SUBREG (IMPLICIT_DEF), GPR32:$Rn, sub_32)),
sub_32)>;
def : Pat<(i32 (combine_op GPR32:$Rn, (trunc (int_aarch64_sve_cntp_oneuse (nxv2i1 PPRAny:$pred), (nxv2i1 PPRAny:$pred))))),
(EXTRACT_SUBREG (!cast<Instruction>(NAME # _D) PPRAny:$pred,
- (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32)),
+ (INSERT_SUBREG (IMPLICIT_DEF), GPR32:$Rn, sub_32)),
sub_32)>;
}
@@ -1195,17 +1195,17 @@ multiclass sve_int_pred_pattern_a<bits<3> opc, string asm,
(!cast<Instruction>(NAME) GPR64:$Rdn, sve_pred_enum:$pattern, $imm)>;
def : Pat<(i32 (op GPR32:$Rdn, (i32 (trunc (opcnt (sve_pred_enum:$pattern)))))),
- (EXTRACT_SUBREG (!cast<Instruction>(NAME) (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
+ (EXTRACT_SUBREG (!cast<Instruction>(NAME) (INSERT_SUBREG (IMPLICIT_DEF),
GPR32:$Rdn, sub_32), sve_pred_enum:$pattern, 1),
sub_32)>;
def : Pat<(i32 (op GPR32:$Rdn, (mul (i32 (trunc (opcnt (sve_pred_enum:$pattern)))), (sve_cnt_mul_imm_i32 i32:$imm)))),
- (EXTRACT_SUBREG (!cast<Instruction>(NAME) (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
+ (EXTRACT_SUBREG (!cast<Instruction>(NAME) (INSERT_SUBREG (IMPLICIT_DEF),
GPR32:$Rdn, sub_32), sve_pred_enum:$pattern, $imm),
sub_32)>;
def : Pat<(i32 (op GPR32:$Rdn, (shl (i32 (trunc (opcnt (sve_pred_enum:$pattern)))), (sve_cnt_shl_imm i32:$imm)))),
- (EXTRACT_SUBREG (!cast<Instruction>(NAME) (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
+ (EXTRACT_SUBREG (!cast<Instruction>(NAME) (INSERT_SUBREG (IMPLICIT_DEF),
GPR32:$Rdn, sub_32), sve_pred_enum:$pattern, $imm),
sub_32)>;
}
More information about the llvm-commits
mailing list