[llvm] 0ed7a5a - [AMDGPU] Clean up GFX10 FLAT saddr field definition

Jay Foad via llvm-commits llvm-commits at lists.llvm.org
Fri Mar 15 09:00:31 PDT 2024


Author: Jay Foad
Date: 2024-03-15T15:56:21Z
New Revision: 0ed7a5a9a1d4297e30c7992379ff292cd1aa3828

URL: https://github.com/llvm/llvm-project/commit/0ed7a5a9a1d4297e30c7992379ff292cd1aa3828
DIFF: https://github.com/llvm/llvm-project/commit/0ed7a5a9a1d4297e30c7992379ff292cd1aa3828.diff

LOG: [AMDGPU] Clean up GFX10 FLAT saddr field definition

On GFX10 only, saddr = EXEC_HI (instead of NULL) is use to distinguish
ST mode from other SCRATCH addressing modes. Handle this when defining
the saddr field instead of overriding it in subclasses.

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/FLATInstructions.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/FLATInstructions.td b/llvm/lib/Target/AMDGPU/FLATInstructions.td
index c6a0d6e89f443a..548bbfde408782 100644
--- a/llvm/lib/Target/AMDGPU/FLATInstructions.td
+++ b/llvm/lib/Target/AMDGPU/FLATInstructions.td
@@ -2115,7 +2115,9 @@ class FLAT_Real_gfx10<bits<7> op, FLAT_Pseudo ps> :
 
   let Inst{11-0}  = offset{11-0};
   let Inst{12}    = !if(ps.has_dlc, cpol{CPolBit.DLC}, ps.dlcValue);
-  let Inst{54-48} = !if(ps.enabled_saddr, saddr, 0x7d);
+  let Inst{54-48} = !cond(ps.enabled_saddr : saddr,
+                          !and(ps.is_flat_scratch, !not(ps.has_vaddr)) : EXEC_HI.Index{6-0}, // ST mode
+                          true : SGPR_NULL_gfxpre11.Index{6-0});
   let Inst{55}    = 0;
 }
 
@@ -2143,7 +2145,6 @@ multiclass FLAT_Real_SADDR_RTN_gfx10<bits<7> op> {
 multiclass FLAT_Real_ST_gfx10<bits<7> op> {
   def _ST_gfx10 :
     FLAT_Real_gfx10<op, !cast<FLAT_Pseudo>(NAME#"_ST")> {
-      let Inst{54-48} = EXEC_HI.Index;
       let OtherPredicates = [HasFlatScratchSTMode];
     }
 }


        


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