[clang] [llvm] [RISC-V] Add CSR read/write builtins (PR #85091)

[Wang Pengcheng via llvm-commits]

wangpc-pp wrote:

GCC gained its `__arm_rsr` and `__arm_wsr` support last year (October, 2023): https://gcc.gnu.org/pipermail/gcc-patches/2023-October/631855.html. So there is no stable released GCC version that supports these builtins.
Clang supported these builtins about nine years ago: https://reviews.llvm.org/D9697. But as we know, clang is not the default compiler in most OS distributions. People may not even know these features.
We can see some usages (ignore the gcc/llvm packages) via Debain Code Search: http://codesearch.debian.net/search?q=__arm_rsr&literal=1.
So I think it's mainly a problem left over by history:
```
// Although the ARM ACLE does have a specification for __arm_rsr/__arm_wsr
// for reading and writing to the status registers, they are not implemented
// by GCC, so we need to resort to inline assembly.
```
As for RISCV, the software ecosystem is growing. So I just think we should do the right thing ASAP.

https://github.com/llvm/llvm-project/pull/85091