[llvm] [RISCV] Handle scalable ops with < EEW / 2 narrow types in combineBinOp_VLToVWBinOp_VL (PR #84158)

[Craig Topper via llvm-commits]

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@@ -14112,7 +14102,9 @@ static SDValue combineBinOp_VLToVWBinOp_VL(SDNode *N,
                                            TargetLowering::DAGCombinerInfo &DCI,
                                            const RISCVSubtarget &Subtarget) {
   SelectionDAG &DAG = DCI.DAG;
-  if (DCI.isBeforeLegalize())
+  // Don't perform this until types are legalized and any legal i1 types are
+  // custom lowered to avoid introducing unselectable V{S,Z}EXT_VLs.
+  if (DCI.isBeforeLegalizeOps())
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topperc wrote:

I'm not sure this is 100% reliable. Its theoretically possible for an i1 vector to be created by the DAG combiner after legalize ops. The last DAG combine stage also runs the legalizer on every node as  part of its worklist. So its not illegal for an i1 zext to created as it would get legalized before isel.

https://github.com/llvm/llvm-project/pull/84158