[llvm] [AMDGPU] Allocate i1 argument to SGPRs (PR #72461)

[Jun Wang via llvm-commits]

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@@ -3225,6 +3230,21 @@ SDValue SITargetLowering::LowerCallResult(
       Val = DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), InGlue);
       Chain = Val.getValue(1);
       InGlue = Val.getValue(2);
+
+      // For i1 return value allocated to an SGPR, we want the dst reg for the
+      // above CopyFromReg not to be of VReg_1 when emitting machine code.
+      // This requires creating an addional CopyToReg followed by another
+      // CopyFromReg.
+      if (RVLocs.size() == 1 && VA.getLocVT() == MVT::i1) {
+        const SIRegisterInfo *TRI = Subtarget->getRegisterInfo();
+        MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
+
+        if (TRI->isSGPRReg(MRI, VA.getLocReg())) {
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jwanggit86 wrote:

So far only `CC_AMDGPU_Func/RetCC_AMDGPU_Func` have been modified such that i1 arg/return are put in SGPRs. Therefore, other calling conv functions still use VGPRs. Do you want all the others to be changed as well?

https://github.com/llvm/llvm-project/pull/72461