[llvm] [DAG] Matched FixedWidth pattern for ISD::AVGFLOORU (PR #84903)

[Shourya Goel via llvm-commits]

================
@@ -859,6 +859,36 @@ define <4 x i32> @urhadd_v4i32(<4 x i32> %x) {
   ret <4 x i32> %r
 }
 
+define i4 @uhadd_fixedwidth_i4(i4 %a0, i4 %a1)  {
+; CHECK-LABEL: uhadd_fixedwidth_i4:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    eor w8, w0, w1
+; CHECK-NEXT:    and w9, w0, w1
+; CHECK-NEXT:    and w8, w8, #0xe
+; CHECK-NEXT:    add w0, w9, w8, lsr #1
+; CHECK-NEXT:    ret
+  %and = and i4 %a0, %a1
+  %xor = xor i4 %a0, %a1
+  %srl = lshr i4 %xor, 1
+  %res = add i4 %and, %srl
+  ret i4 %res
+}
+
+define <4 x i32> @uhadd_fixedwidth_v4i32(<4 x i32> %a0, <4 x i32> %a1)  {
+; CHECK-LABEL: uhadd_fixedwidth_v4i32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and v2.16b, v0.16b, v1.16b
+; CHECK-NEXT:    eor v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    usra v2.4s, v0.4s, #1
+; CHECK-NEXT:    mov v0.16b, v2.16b
----------------
Sh0g0-1758 wrote:

Yes, indeed but whenever I run the update_llc_test_checks.py on the test case : 

```asm
define <4 x i32> @uhadd_fixedwidth_v4i32(<4 x i32> %a0, <4 x i32> %a1)  {
  %and = and <4 x i32> %a0, %a1
  %xor = xor <4 x i32> %a0, %a1
  %srl = lshr <4 x i32> %xor, <i32 1,i32 1,i32 1,i32 1>
  %res = add <4 x i32> %and, %srl
  ret <4 x i32> %res
}
```

I get the same check assertions for both when I add the change in VT to vector type and when I don't. The only difference is that in the former, the tests pass. Is there something else that needs to be done to generate the correct assertions or is there some change in the original DAGCombiner.cpp required apart from the vector Type, because regardless of it, the assertions I am getting are the same. 

https://github.com/llvm/llvm-project/pull/84903