[llvm] [ARM] Validate STREX instruction in the assembler (PR #85074)

[Tomas Matheson via llvm-commits]

================
@@ -7629,6 +7629,39 @@ bool ARMAsmParser::validateInstruction(MCInst &Inst,
     }
     return false;
   }
+  case ARM::t2STREXB:
+  case ARM::t2STREXH:
+  case ARM::t2STREX:
+  case ARM::STREXB:
+  case ARM::STREXH:
+  case ARM::STREX:
+  case ARM::STREXD: {
+    unsigned Rd = MRI->getEncodingValue(Inst.getOperand(0).getReg());
+    unsigned Rm = MRI->getEncodingValue(Inst.getOperand(1).getReg());
+    unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg());
+
+    if (Rd == 15 || Rm == 15 || Rn == 15)
+      return Error(Operands[3]->getStartLoc(), "operand can't be R15");
----------------
tmatheson-arm wrote:

I'm not sure we handle other cases of UNPREDICTABLE, but it seems like these should be warnings rather than errors, since it is possible to actually emit the encoding.

https://github.com/llvm/llvm-project/pull/85074