[llvm] [ARM][TableGen][MC] Change the ARM mnemonic operands to be optional for ASM parsing (PR #83436)

[Alfie Richards via llvm-commits]

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@@ -1564,6 +1562,10 @@ class AsmParser {
   // method shall be called for all operands as opposed to only those
   // that have their own specified custom parsers.
   bit CallCustomParserForAllOperands = false;
+
+  // PreferSmallerInstructions - Should the assembly matcher prefer the smaller
+  // instructions.
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AlfieRichardsArm wrote:

Yes I agree with @kosarev also. The ARM backend has a massive number of ambiguous matchables (some are exact duplicate aliases, some are meaningfully different) that we rely on the stable sort to not change the order of. 
I have a patch to remove a handful of completely redundant matchables I'll clean up and send upstream at some point. 

As discussed in https://github.com/llvm/llvm-project/pull/84483 I do think there is a case to order by predicates (similar to current sorting by register classes), however there isn't a good way to do this that I can see.

https://github.com/llvm/llvm-project/pull/83436