[llvm] 65f5e2c - [RISC-V] Add another missing cast in .td file (#85055)

[via llvm-commits]

Author: Nemanja Ivanovic
Date: 2024-03-14T10:29:16+01:00
New Revision: 65f5e2c4070f22ab7a1617c798b4c61baa9b39a8

URL: https://github.com/llvm/llvm-project/commit/65f5e2c4070f22ab7a1617c798b4c61baa9b39a8
DIFF: https://github.com/llvm/llvm-project/commit/65f5e2c4070f22ab7a1617c798b4c61baa9b39a8.diff

LOG: [RISC-V] Add another missing cast in .td file (#85055)

Another instance where we produce an instruction that defines a vreg
with an i32 value.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfo.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index e753c1f1add0c6..966cdc433d0fd4 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -1405,7 +1405,8 @@ multiclass BccPat<CondCode Cond, RVInstB Inst> {
 
 class BrccCompressOpt<CondCode Cond, RVInstB Inst>
     : Pat<(riscv_brcc GPR:$lhs, simm12_no6:$Constant, Cond, bb:$place),
-          (Inst (ADDI GPR:$lhs, (NegImm simm12:$Constant)), (XLenVT X0), bb:$place)>;
+          (Inst (XLenVT (ADDI GPR:$lhs, (NegImm simm12:$Constant))),
+                (XLenVT X0), bb:$place)>;
 
 defm : BccPat<SETEQ, BEQ>;
 defm : BccPat<SETNE, BNE>;