[llvm] [DAG] Matched FixedWidth pattern for ISD::AVGFLOORU (PR #84903)

[Shourya Goel via llvm-commits]

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@@ -2821,6 +2821,47 @@ SDValue DAGCombiner::visitADDLike(SDNode *N) {
   return SDValue();
 }
 
+// Attempt to form avgflooru(A, B) from add(and(A, B), lshr(xor(A, B), 1))
+static SDValue combineFixedwidthToAVGFLOORU(SDNode *N, SelectionDAG &DAG) {
+  assert(N->getOpcode() == ISD::ADD && "ADD node is required here");
+  SDValue And = N->getOperand(0);
+  SDValue Lshr = N->getOperand(1);
+  if (And.getOpcode() == ISD::SRL && Lshr.getOpcode() == ISD::AND) {
+    SDValue temp = And;
+    And = Lshr;
+    Lshr = temp;
+  } else if (And.getOpcode() != ISD::AND || Lshr.getOpcode() != ISD::SRL)
+    return SDValue();
+  SDValue Xor = Lshr.getOperand(0);
+  if (Xor.getOpcode() != ISD::XOR)
+    return SDValue();
+  SDValue And1 = And.getOperand(0);
+  SDValue And2 = And.getOperand(1);
+  SDValue Xor1 = Xor.getOperand(0);
+  SDValue Xor2 = Xor.getOperand(1);
+  if (And1 == Xor2 && And2 == Xor1) {
+    SDValue temp = And1;
+    And1 = And2;
+    And2 = temp;
+  } else if (And1 != Xor1 || And2 != Xor2)
+    return SDValue();
+  // Is the right shift using an immediate value of 1?
+  ConstantSDNode *N1C = isConstOrConstSplat(Lshr.getOperand(1));
+  if (!N1C or N1C->getAPIntValue() != 1)
+    return SDValue();
+  EVT VT = And1.getValueType();
+  EVT NVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
+  if (VT.isVector())
+    VT = EVT::getVectorVT(*DAG.getContext(), NVT, VT.getVectorElementCount());
+  else
+    VT = NVT;
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Sh0g0-1758 wrote:

`Or1.getValueType()` ? Yes, that is what fixedwidth means and was also pointed out by RKSimon but the tests don't pass unless I adjust the type. 

https://github.com/llvm/llvm-project/pull/84903