[llvm] [AArch64][GlobalISel] Take abs scalar codegen closer to SDAG (PR #84886)

[Madhur Amilkanthwar via llvm-commits]

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@@ -8219,6 +8223,19 @@ LegalizerHelper::lowerAbsToMaxNeg(MachineInstr &MI) {
   return Legalized;
 }
 
+LegalizerHelper::LegalizeResult
+LegalizerHelper::lowerAbsToCNeg(MachineInstr &MI) {
+  Register SrcReg = MI.getOperand(1).getReg();
+  Register DestReg = MI.getOperand(0).getReg();
+  LLT Ty = MRI.getType(SrcReg);
+  auto Zero = MIRBuilder.buildConstant(Ty, 0).getReg(0);
+  auto Sub = MIRBuilder.buildSub(Ty, Zero, SrcReg).getReg(0);
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madhur13490 wrote:

Done. Thanks!

https://github.com/llvm/llvm-project/pull/84886