[llvm] [AArch64][GlobalISel] Take abs scalar codegen closer to SDAG (PR #84886)

[David Green via llvm-commits]

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@@ -3914,8 +3914,12 @@ LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT LowerHintTy) {
   case G_SSHLSAT:
   case G_USHLSAT:
     return lowerShlSat(MI);
-  case G_ABS:
+  case G_ABS: {
+    LLT Ty = MRI.getType(MI.getOperand(0).getReg());
+    if (LI.isLegalOrCustom({G_ABS, Ty}))
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davemgreen wrote:

I think the problem might be that there is no good way with the isLegal calls to check if there is a single instruction that does "select and conditional neg" at the same time, in the way csneg would do.

https://github.com/llvm/llvm-project/pull/84886