[llvm] LivePhysRegs to LiveRegUnits (PR #85162)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-arm

Author: AtariDreams (AtariDreams)

<details>
<summary>Changes</summary>

More conversions from LivePhysRegs to LiveRegUnits

---
Full diff: https://github.com/llvm/llvm-project/pull/85162.diff


2 Files Affected:

- (modified) llvm/lib/Target/ARM/ARMConstantIslandPass.cpp (+7-5) 
- (modified) llvm/lib/Target/SystemZ/SystemZPostRewrite.cpp (+9-6) 


``````````diff
diff --git a/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp b/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
index 7a3ba5870bc6df..8cd520c4e42aa8 100644
--- a/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
+++ b/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
@@ -27,7 +27,7 @@
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/Statistic.h"
 #include "llvm/ADT/StringRef.h"
-#include "llvm/CodeGen/LivePhysRegs.h"
+#include "llvm/CodeGen/LiveRegUnits.h"
 #include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/CodeGen/MachineConstantPool.h"
 #include "llvm/CodeGen/MachineDominators.h"
@@ -990,7 +990,7 @@ MachineBasicBlock *ARMConstantIslands::splitBlockBeforeInstr(MachineInstr *MI) {
   MachineBasicBlock *OrigBB = MI->getParent();
 
   // Collect liveness information at MI.
-  LivePhysRegs LRs(*MF->getSubtarget().getRegisterInfo());
+  LiveRegUnits LRs(*MF->getSubtarget().getRegisterInfo());
   LRs.addLiveOuts(*OrigBB);
   auto LivenessEnd = ++MachineBasicBlock::iterator(MI).getReverse();
   for (MachineInstr &LiveMI : make_range(OrigBB->rbegin(), LivenessEnd))
@@ -1026,9 +1026,11 @@ MachineBasicBlock *ARMConstantIslands::splitBlockBeforeInstr(MachineInstr *MI) {
 
   // Update live-in information in the new block.
   MachineRegisterInfo &MRI = MF->getRegInfo();
-  for (MCPhysReg L : LRs)
-    if (!MRI.isReserved(L))
-      NewBB->addLiveIn(L);
+  const llvm::BitVector &bitVector = LRs.getBitVector();
+  for (unsigned RegUnit = 0; RegUnit < bitVector.size(); ++RegUnit) {
+    if (bitVector.test(RegUnit)) {
+    if (!MRI.isReserved(RegUnit))
+      NewBB->addLiveIn(RegUnit);
 
   // Update internal data structures to account for the newly inserted MBB.
   // This is almost the same as updateForInsertedWaterBlock, except that
diff --git a/llvm/lib/Target/SystemZ/SystemZPostRewrite.cpp b/llvm/lib/Target/SystemZ/SystemZPostRewrite.cpp
index e15f9027cc2095..fed801a698972d 100644
--- a/llvm/lib/Target/SystemZ/SystemZPostRewrite.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZPostRewrite.cpp
@@ -17,7 +17,7 @@
 #include "SystemZInstrInfo.h"
 #include "SystemZSubtarget.h"
 #include "llvm/ADT/Statistic.h"
-#include "llvm/CodeGen/LivePhysRegs.h"
+#include "llvm/CodeGen/LiveRegUnits.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 using namespace llvm;
@@ -161,7 +161,7 @@ bool SystemZPostRewrite::expandCondMove(MachineBasicBlock &MBB,
   assert(DestReg == MI.getOperand(1).getReg() &&
          "Expected destination and first source operand to be the same.");
 
-  LivePhysRegs LiveRegs(TII->getRegisterInfo());
+  LiveRegUnits LiveRegs(TII->getRegisterInfo());
   LiveRegs.addLiveOuts(MBB);
   for (auto I = std::prev(MBB.end()); I != MBBI; --I)
     LiveRegs.stepBackward(*I);
@@ -171,15 +171,18 @@ bool SystemZPostRewrite::expandCondMove(MachineBasicBlock &MBB,
   MF.insert(std::next(MachineFunction::iterator(MBB)), RestMBB);
   RestMBB->splice(RestMBB->begin(), &MBB, MI, MBB.end());
   RestMBB->transferSuccessors(&MBB);
-  for (MCPhysReg R : LiveRegs)
-    RestMBB->addLiveIn(R);
+  const llvm::BitVector &bitVector = LiveRegs.getBitVector();
+  for (unsigned RegUnit = 0; RegUnit < bitVector.size(); ++RegUnit) {
+    if (bitVector.test(RegUnit))
+      RestMBB->addLiveIn(RegUnit);
 
   // Create a new block MoveMBB to hold the move instruction.
   MachineBasicBlock *MoveMBB = MF.CreateMachineBasicBlock(BB);
   MF.insert(std::next(MachineFunction::iterator(MBB)), MoveMBB);
   MoveMBB->addLiveIn(SrcReg);
-  for (MCPhysReg R : LiveRegs)
-    MoveMBB->addLiveIn(R);
+  for (unsigned RegUnit = 0; RegUnit < bitVector.size(); ++RegUnit) {
+    if (bitVector.test(RegUnit))
+      RestMBB->addLiveIn(RegUnit);
 
   // At the end of MBB, create a conditional branch to RestMBB if the
   // condition is false, otherwise fall through to MoveMBB.

``````````

</details>


https://github.com/llvm/llvm-project/pull/85162