[llvm] [AArch64] Support scalable offsets with isLegalAddressingMode (PR #83255)

[Graham Hunter via llvm-commits]

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@@ -16374,15 +16374,31 @@ bool AArch64TargetLowering::isLegalAddressingMode(const DataLayout &DL,
 
   if (Ty->isScalableTy()) {
     if (isa<ScalableVectorType>(Ty)) {
+      // See if we have a foldable vscale-based offset, for vector types which
+      // are either legal or smaller than the minimum; more work will be
+      // required if we need to consider addressing for types which need
+      // legalization by splitting.
+      uint64_t VecNumBytes = DL.getTypeSizeInBits(Ty).getKnownMinValue() / 8;
+      if (AM.HasBaseReg && !AM.BaseOffs && AM.ScalableOffset && !AM.Scale &&
+          (AM.ScalableOffset % VecNumBytes == 0) && VecNumBytes <= 16 &&
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huntergr-arm wrote:

I check that the minimum number of bytes is <= 16 (so at most one legal SVE vector) and that it's a power-of-two. I would have restricted it to legal types only, but I've seen several loops which extended a smaller type; so a <vscale x 2 x i8> might be just fine as a type here to determine whether an addressing mode is legal, though it will be extended to <vscale x 2 x i64> in the actual register. We just care about the offset in memory, and from my reading of the ISA the `#imm, mul vl` addressing goes by the in-memory size.

I have indeed ignored larger-than-legal types for this initial work, as I don't have a motivating example where I need to improve addressing for them.

https://github.com/llvm/llvm-project/pull/83255