[llvm] [DAG] Matched FixedWidth pattern for ISD::AVGFLOORU (PR #84903)

[Simon Pilgrim via llvm-commits]

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@@ -2821,6 +2821,38 @@ SDValue DAGCombiner::visitADDLike(SDNode *N) {
   return SDValue();
 }
 
+// Attempt to form ext(avgflooru(A, B)) from add(and(A, B), lshr(xor(A, B), 1))
+static SDValue combineFixedwidthToAVG(SDNode *N, SelectionDAG &DAG) {
+  assert(N->getOpcode() == ISD::ADD && "ADD node is required here");
+  SDValue And = N->getOperand(0);
+  SDValue Lshr = N->getOperand(1);
+  if (And.getOpcode() != ISD::AND || Lshr.getOpcode() != ISD::SRL)
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RKSimon wrote:

I'll get m_And / mXor / m_Or added shortly

https://github.com/llvm/llvm-project/pull/84903