[llvm] [RISC-V] Add another missing cast in .td file (PR #85055)

[Nemanja Ivanovic via llvm-commits]

https://github.com/nemanjai created https://github.com/llvm/llvm-project/pull/85055

Another instance where we produce an instruction that defines a vreg with an i32 value.

>From 62b4fa8f5d08f87d7ccac878e4cc363ce1143ba2 Mon Sep 17 00:00:00 2001
From: Nemanja Ivanovic <nemanja at synopsys.com>
Date: Wed, 13 Mar 2024 11:27:10 +0100
Subject: [PATCH] [RISC-V] Add another missing cast in .td file

Another instance where we produce an instruction that defines
a vreg with an i32 value.
---
 llvm/lib/Target/RISCV/RISCVInstrInfo.td | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index e753c1f1add0c6..966cdc433d0fd4 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -1405,7 +1405,8 @@ multiclass BccPat<CondCode Cond, RVInstB Inst> {
 
 class BrccCompressOpt<CondCode Cond, RVInstB Inst>
     : Pat<(riscv_brcc GPR:$lhs, simm12_no6:$Constant, Cond, bb:$place),
-          (Inst (ADDI GPR:$lhs, (NegImm simm12:$Constant)), (XLenVT X0), bb:$place)>;
+          (Inst (XLenVT (ADDI GPR:$lhs, (NegImm simm12:$Constant))),
+                (XLenVT X0), bb:$place)>;
 
 defm : BccPat<SETEQ, BEQ>;
 defm : BccPat<SETNE, BNE>;