[llvm] [DAG] Matched Fixedwidth Pattern for ISD::AVGCEILU (PR #85031)

[Shourya Goel via llvm-commits]

================
@@ -2529,6 +2529,39 @@ static SDValue foldAddSubBoolOfMaskedVal(SDNode *N, SelectionDAG &DAG) {
   return DAG.getNode(IsAdd ? ISD::SUB : ISD::ADD, DL, VT, C1, LowBit);
 }
 
+// Attempt to form ext(avgceilu(A, B)) from sub(or(A, B), lshr(xor(A, B), 1))
----------------
Sh0g0-1758 wrote:

done. 

https://github.com/llvm/llvm-project/pull/85031