[llvm] Matched some basic ISD::AVGFLOORU patterns (PR #84903)

[Shourya Goel via llvm-commits]

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@@ -859,6 +859,21 @@ define <4 x i32> @urhadd_v4i32(<4 x i32> %x) {
   ret <4 x i32> %r
 }
 
+define <4 x i32> @fixedwidth(<4 x i32> %a0, <4 x i32> %a1)  {
+; CHECK-LABEL: fixedwidth:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and v2.16b, v0.16b, v1.16b
+; CHECK-NEXT:    eor v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    usra v2.4s, v0.4s, #1
+; CHECK-NEXT:    mov v0.16b, v2.16b
+; CHECK-NEXT:    ret
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Sh0g0-1758 wrote:

Well yes, but isn't integer VT different than vector VT? Please pardon my silly questions. From my understanding, FixedWidth means not extending the bits as we would have done in ADD to prevent overflow. 

https://github.com/llvm/llvm-project/pull/84903