[llvm] Matched some basic ISD::AVGFLOORU patterns (PR #84903)

[Shourya Goel via llvm-commits]

================
@@ -859,6 +859,21 @@ define <4 x i32> @urhadd_v4i32(<4 x i32> %x) {
   ret <4 x i32> %r
 }
 
+define <4 x i32> @fixedwidth(<4 x i32> %a0, <4 x i32> %a1)  {
+; CHECK-LABEL: fixedwidth:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and v2.16b, v0.16b, v1.16b
+; CHECK-NEXT:    eor v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    usra v2.4s, v0.4s, #1
+; CHECK-NEXT:    mov v0.16b, v2.16b
+; CHECK-NEXT:    ret
----------------
Sh0g0-1758 wrote:

My understanding of implementing vector type is limited to `TargetLowering.cpp` for now in which we have used the demanded masks for vectors while in `DAGCombiner.cpp` we have simply returned SDValue(). But I suppose we can implement vectors using this? : 

```cpp
  EVT NVT = EVT::getIntegerVT(*DAG.getContext(), llvm::bit_ceil(VT.getScalarSizeInBits()));
  if (VT.isVector())
    NVT = EVT::getVectorVT(*DAG.getContext(), NVT, VT.getVectorElementCount());
```

https://github.com/llvm/llvm-project/pull/84903