[llvm] [RISCV] Support `llvm.masked.compressstore` intrinsic (PR #83457)

[Kolya Panchenko via llvm-commits]

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@@ -1620,3 +1620,15 @@ bool RISCVTTIImpl::isLSRCostLess(const TargetTransformInfo::LSRCost &C1,
                   C2.NumIVMuls, C2.NumBaseAdds,
                   C2.ScaleCost, C2.ImmCost, C2.SetupCost);
 }
+
+bool RISCVTTIImpl::isLegalMaskedCompressStore(Type *DataTy, Align Alignment) {
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nikolaypanchenko wrote:

Unlike x86, if store is done via separate instruction and requires masking, RVV's implementation does not require masking/predication due to tweaked VL.

https://github.com/llvm/llvm-project/pull/83457