[llvm] [AArch64][GlobalISel] Legalize Insert vector element (PR #81453)

[David Green via llvm-commits]

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@@ -883,9 +883,15 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
       .clampMaxNumElements(1, p0, 2);
 
   getActionDefinitionsBuilder(G_INSERT_VECTOR_ELT)
-      .legalIf(typeInSet(0, {v16s8, v8s8, v8s16, v4s16, v4s32, v2s32, v2s64}))
+      .legalIf(
+          typeInSet(0, {v16s8, v8s8, v8s16, v4s16, v4s32, v2s32, v2s64, v2p0}))
       .moreElementsToNextPow2(0)
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davemgreen wrote:

> There is no notion of fpr and gpr in the legalizer. We have to state the legal types for operations. The issue comes up with untyped operations, like e.g., G_SELECT, G_INSERT_VETOR_ELT, G_BUILD_VECTOR, ...
> 
> For typed operations, we need no floats in the LLT. s16 is legal for G_FADD, but it is not legal for G_ADD. In the later case, it would have been an i16.

I'm not sure I am understanding your comment, but I think I agree with the first half.

For the second half the problem is not between G_FADD and G_ADD, it is between G_FADD with fp16 and G_FADD with bf16. They both have the same s16 sized operands, but there is currently no way to tell them apart in GISel.

https://github.com/llvm/llvm-project/pull/81453