[llvm] Matched some basic ISD::AVGFLOORU patterns (PR #84903)

[Simon Pilgrim via llvm-commits]

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@@ -0,0 +1,11 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=aarch64 | FileCheck %s
+
+define i4 @fixedwidth(i4 %a0, i4 %a1)  {
+; CHECK-LABEL: fixedwidth:
+  %and = and i4 %a0, %a1
+  %xor = xor i4 %a0, %a1
+  %srl = lshr i4 %xor, 1
+  %res = add i4 %and, %srl
+  ret i4 %res
+}
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RKSimon wrote:

No need for a new file - you can add these to hadd-combine.ll as that already has many avg tests (hadd is short for halving add on ARM).

Don't use i4 (I just made the types tiny so alive2 wouldn't timeout doing the exhaustive tests) - better to use vector types.

You will also need to use the llvm-project\llvm\utils\update_llc_test_checks.py script to regenerate the test checks


https://github.com/llvm/llvm-project/pull/84903