[llvm] [AArch64][SVE2] Generate SVE2 BSL instruction in LLVM for bit-twiddling. (PR #83514)

[Paul Walker via llvm-commits]

================
@@ -17660,23 +17656,32 @@ static SDValue tryCombineToBSL(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
     for (int j = 1; j >= 0; --j) {
       BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(i));
       BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(j));
-      if (!BVN0 || !BVN1)
+      APInt Val1, Val2;
+      if ((!BVN0 || !BVN1) &&
+          (!ISD::isConstantSplatVector(N0->getOperand(i).getNode(), Val1) ||
+           !ISD::isConstantSplatVector(N1->getOperand(j).getNode(), Val2)))
----------------
paulwalker-arm wrote:

This is subjective so it's up to you but if we're dismissing the possibility of mixing build vectors and splat vectors then it would be simpler to just enter the loops with:
```
APInt Val1, Val2;
if (ISD::isConstantSplatVector(N0->getOperand(i).getNode(), Val1) &&
    ISD::isConstantSplatVector(N1->getOperand(j).getNode(), Val2) &&
    ((BitMask & ~Val1.getZExtValue()) == Val2.getZExtValue()))
  return DAG.getNode(AArch64ISD::BSP, ....
    
```

https://github.com/llvm/llvm-project/pull/83514