[llvm] AMDGPU: Add an argument to DS_Real_gfx12 to disable alias, NFC (PR #84717)
Changpeng Fang via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 11 11:32:47 PDT 2024
https://github.com/changpeng updated https://github.com/llvm/llvm-project/pull/84717
>From cc64e8850c8242ebb14db1fd5d592c91c11b5208 Mon Sep 17 00:00:00 2001
From: Changpeng Fang <changpeng.fang at amd.com>
Date: Sun, 10 Mar 2024 21:33:37 -0700
Subject: [PATCH 1/2] AMDGPU: Add an argument to DS_Real_gfx12 to disable
alias, NFC
This is for cased that we simply want to rename from ps.Mnemonic,
but ps.Mnemonic itself is not supported as an alias.
---
llvm/lib/Target/AMDGPU/DSInstructions.td | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/DSInstructions.td b/llvm/lib/Target/AMDGPU/DSInstructions.td
index a84227ebf506fe..2a02d7f95b3c8c 100644
--- a/llvm/lib/Target/AMDGPU/DSInstructions.td
+++ b/llvm/lib/Target/AMDGPU/DSInstructions.td
@@ -1210,13 +1210,13 @@ class Base_DS_Real_gfx6_gfx7_gfx10_gfx11_gfx12<bits<8> op, DS_Pseudo ps, int ef,
// GFX12.
//===----------------------------------------------------------------------===//
-multiclass DS_Real_gfx12<bits<8> op, string name = !tolower(NAME)> {
+multiclass DS_Real_gfx12<bits<8> op, string name = !tolower(NAME), int needAlias = true> {
defvar ps = !cast<DS_Pseudo>(NAME);
let AssemblerPredicate = isGFX12Plus, DecoderNamespace = "GFX12" in
def _gfx12 :
Base_DS_Real_gfx6_gfx7_gfx10_gfx11_gfx12<op, ps, SIEncodingFamily.GFX12,
name, /*hasGDS=*/false>;
- if !ne(ps.Mnemonic, name) then
+ if !and(needAlias, !ne(ps.Mnemonic, name)) then
def : MnemonicAlias<ps.Mnemonic, name>, Requires<[isGFX12Plus]>;
}
>From 0ffc17484b4710bd45c2740c563d95804cc4396c Mon Sep 17 00:00:00 2001
From: Changpeng Fang <changpeng.fang at amd.com>
Date: Mon, 11 Mar 2024 11:31:35 -0700
Subject: [PATCH 2/2] AMDGPU: Make a small change of the type from int to bit
---
llvm/lib/Target/AMDGPU/DSInstructions.td | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/AMDGPU/DSInstructions.td b/llvm/lib/Target/AMDGPU/DSInstructions.td
index 2a02d7f95b3c8c..cc763df5a4760b 100644
--- a/llvm/lib/Target/AMDGPU/DSInstructions.td
+++ b/llvm/lib/Target/AMDGPU/DSInstructions.td
@@ -1210,7 +1210,7 @@ class Base_DS_Real_gfx6_gfx7_gfx10_gfx11_gfx12<bits<8> op, DS_Pseudo ps, int ef,
// GFX12.
//===----------------------------------------------------------------------===//
-multiclass DS_Real_gfx12<bits<8> op, string name = !tolower(NAME), int needAlias = true> {
+multiclass DS_Real_gfx12<bits<8> op, string name = !tolower(NAME), bit needAlias = true> {
defvar ps = !cast<DS_Pseudo>(NAME);
let AssemblerPredicate = isGFX12Plus, DecoderNamespace = "GFX12" in
def _gfx12 :
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