[clang] [llvm] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1 instructions. (PR #83896)

[Garvit Gupta via llvm-commits]

quic-garvgupt wrote:

Also, I think we might need to update the extensions in the `RISCVProcessors.td` file under SIFIVE_S76 microcontroller?

https://github.com/llvm/llvm-project/pull/83896