[llvm] [ARM] Resolve FIXME: Transform "(and (shl x, c2), c1)" into "(shl (and x, c1>>c2), c2)" (PR #82120)
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Mon Mar 11 11:06:02 PDT 2024
https://github.com/AtariDreams updated https://github.com/llvm/llvm-project/pull/82120
>From 4eb467fab4b9e8bc34de7ae8c444c099fbe7c381 Mon Sep 17 00:00:00 2001
From: Rose <83477269+AtariDreams at users.noreply.github.com>
Date: Sat, 17 Feb 2024 11:38:21 -0500
Subject: [PATCH] [ARM] Resolve FIXME: Transform "(and (shl x, c2), c1)" into
"(shl (and x, c1>>c2), c2)"
Transform "(and (shl x, c2), c1)" into "(shl (and x, c1>>c2), c2)" if "c1 >> c2" is a cheaper immediate than "c1" using HasLowerConstantMaterializationCost.
---
llvm/lib/Target/ARM/ARMISelLowering.cpp | 14 +++++++++++---
llvm/test/CodeGen/Thumb/shift-and.ll | 5 ++---
2 files changed, 13 insertions(+), 6 deletions(-)
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index dc81178311b6d8..1525b7915f8cdd 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -14386,9 +14386,17 @@ static SDValue CombineANDShift(SDNode *N,
}
}
- // FIXME: Transform "(and (shl x, c2) c1)" ->
- // "(shl (and x, c1>>c2), c2)" if "c1 >> c2" is a cheaper immediate than
- // c1.
+ // Transform "(and (shl x, c2) c1)" into "(shl (and x, c1>>c2), c2)"
+ // if "c1 >> c2" is a cheaper immediate than "c1"
+ if (LeftShift &&
+ HasLowerConstantMaterializationCost(C1 >> C2, C1, Subtarget)) {
+
+ SDValue And = DAG.getNode(ISD::AND, DL, MVT::i32, N0->getOperand(0),
+ DAG.getConstant(C1 >> C2, DL, MVT::i32));
+ return DAG.getNode(ISD::SHL, DL, MVT::i32, And,
+ DAG.getConstant(C2, DL, MVT::i32));
+ }
+
return SDValue();
}
diff --git a/llvm/test/CodeGen/Thumb/shift-and.ll b/llvm/test/CodeGen/Thumb/shift-and.ll
index e5fee86343b0ed..a8a09dbe1b7390 100644
--- a/llvm/test/CodeGen/Thumb/shift-and.ll
+++ b/llvm/test/CodeGen/Thumb/shift-and.ll
@@ -70,9 +70,8 @@ define i32 @test6(i32 %x) {
; CHECK-LABEL: test6:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: movs r1, #5
-; CHECK-NEXT: lsls r1, r1, #29
-; CHECK-NEXT: lsls r0, r0, #29
-; CHECK-NEXT: ands r0, r1
+; CHECK-NEXT: ands r1, r0
+; CHECK-NEXT: lsls r0, r1, #29
; CHECK-NEXT: bx lr
entry:
%0 = shl i32 %x, 29
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