[llvm] [InstCombine] Optimize x * !x to 0 for vector #84608 (PR #84792)

[via llvm-commits]

https://github.com/SahilPatidar created https://github.com/llvm/llvm-project/pull/84792

Resolve #84608 

>From 4af7e773e718b61887aafc84f677c4c21e764624 Mon Sep 17 00:00:00 2001
From: SahilPatidar <patidarsahil2001 at gmail.com>
Date: Mon, 11 Mar 2024 15:42:26 +0530
Subject: [PATCH] [InstCombine] Optimize x * !x to 0 for vector #84608

---
 .../InstCombine/InstCombineMulDivRem.cpp         | 16 ++++++++++++++++
 llvm/test/Transforms/InstCombine/mul.ll          | 10 ++++++++++
 2 files changed, 26 insertions(+)

diff --git a/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp b/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
index 0bd4b6d1a835af..62ec0526ebd800 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
@@ -198,6 +198,22 @@ Instruction *InstCombinerImpl::visitMul(BinaryOperator &I) {
   if (SimplifyAssociativeOrCommutative(I))
     return &I;
 
+  // mul (sext (icmp eq x, 0)), x -> 0
+  Value *SExtOp, *V0;
+  if ((match(Op0, m_SExt(m_Value(SExtOp))) && match(Op1, m_Value(V0))) ||
+      (match(Op1, m_SExt(m_Value(SExtOp))) && match(Op0, m_Value(V0)))) {
+    Constant *CV;
+    ICmpInst::Predicate Pred;
+    Value *V1;
+    const APInt *IV;
+    if ((match(SExtOp, m_ICmp(Pred, m_Value(V1), m_Constant(CV))) ||
+         match(SExtOp, m_ICmp(Pred, m_Constant(CV), m_Value(V1)))) &&
+        Pred == ICmpInst::Predicate::ICMP_EQ && match(CV, m_APInt(IV)) &&
+        *IV == 0 && V0 == V1) {
+      return replaceInstUsesWith(I, CV);
+    }
+  }
+
   if (Instruction *X = foldVectorBinop(I))
     return X;
 
diff --git a/llvm/test/Transforms/InstCombine/mul.ll b/llvm/test/Transforms/InstCombine/mul.ll
index e7141d7c25ad21..24f580cee79190 100644
--- a/llvm/test/Transforms/InstCombine/mul.ll
+++ b/llvm/test/Transforms/InstCombine/mul.ll
@@ -2049,3 +2049,13 @@ define i32 @zext_negpow2_use(i8 %x) {
   %r = mul i32 %zx, -16777216 ; -1 << 24
   ret i32 %r
 }
+
+define <4 x i32> @mul_icmp_with_zero(<4 x i32> %x) {
+; CHECK-LABEL: @mul_icmp_with_zero(
+; CHECK-NEXT:    ret <4 x i32> zeroinitializer
+;
+  %cmp = icmp eq <4 x i32> %x, zeroinitializer
+  %sext = sext <4 x i1> %cmp to <4 x i32>
+  %mul = mul <4 x i32> %sext, %x
+  ret <4 x i32> %mul
+}