[llvm] [X86][AVX] Fix handling of out-of-bounds shift amounts in AVX2 vector shift nodes (PR #84426)

[Simon Pilgrim via llvm-commits]

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@@ -28927,6 +28927,9 @@ SDValue X86TargetLowering::LowerWin64_INT128_TO_FP(SDValue Op,
 // supported by the Subtarget
 static bool supportedVectorShiftWithImm(EVT VT, const X86Subtarget &Subtarget,
                                         unsigned Opcode) {
+  assert(Opcode == ISD::SHL || Opcode == ISD::SRA || Opcode == ISD::SRL &&
+        "Unexpected Opcode!");
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RKSimon wrote:

Please rebase as I already added these asserts at 7b90a67fe717338f7ae4e53f6b97d0f29bacde8e

https://github.com/llvm/llvm-project/pull/84426