[llvm] 63a5dc4 - [CodeGen] Do not pass MF into MachineRegisterInfo methods. NFC. (#84770)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 11 08:35:09 PDT 2024
Author: Jay Foad
Date: 2024-03-11T15:35:05Z
New Revision: 63a5dc4aedaf8a4b26e536afb22612b4d69100bf
URL: https://github.com/llvm/llvm-project/commit/63a5dc4aedaf8a4b26e536afb22612b4d69100bf
DIFF: https://github.com/llvm/llvm-project/commit/63a5dc4aedaf8a4b26e536afb22612b4d69100bf.diff
LOG: [CodeGen] Do not pass MF into MachineRegisterInfo methods. NFC. (#84770)
MachineRegisterInfo already knows the MF so there is no need to pass it
in as an argument.
Added:
Modified:
llvm/include/llvm/CodeGen/MachineRegisterInfo.h
llvm/lib/CodeGen/MIRParser/MIRParser.cpp
llvm/lib/CodeGen/MachineOutliner.cpp
llvm/lib/CodeGen/MachineRegisterInfo.cpp
llvm/lib/CodeGen/RegAllocBase.cpp
llvm/lib/CodeGen/RegAllocFast.cpp
llvm/lib/CodeGen/RegAllocPBQP.cpp
llvm/lib/CodeGen/TargetLoweringBase.cpp
llvm/lib/Target/AArch64/AArch64LowerHomogeneousPrologEpilog.cpp
llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp
llvm/tools/llvm-exegesis/lib/Assembler.cpp
llvm/tools/llvm-reduce/ReducerWorkItem.cpp
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/MachineRegisterInfo.h b/llvm/include/llvm/CodeGen/MachineRegisterInfo.h
index 257643c109ba1c..3f0fc160f9ea4e 100644
--- a/llvm/include/llvm/CodeGen/MachineRegisterInfo.h
+++ b/llvm/include/llvm/CodeGen/MachineRegisterInfo.h
@@ -244,14 +244,13 @@ class MachineRegisterInfo {
bool isUpdatedCSRsInitialized() const { return IsUpdatedCSRsInitialized; }
/// Returns true if a register can be used as an argument to a function.
- bool isArgumentRegister(const MachineFunction &MF, MCRegister Reg) const;
+ bool isArgumentRegister(MCRegister Reg) const;
/// Returns true if a register is a fixed register.
- bool isFixedRegister(const MachineFunction &MF, MCRegister Reg) const;
+ bool isFixedRegister(MCRegister Reg) const;
/// Returns true if a register is a general purpose register.
- bool isGeneralPurposeRegister(const MachineFunction &MF,
- MCRegister Reg) const;
+ bool isGeneralPurposeRegister(MCRegister Reg) const;
/// Disables the register from the list of CSRs.
/// I.e. the register will not appear as part of the CSR mask.
@@ -930,7 +929,7 @@ class MachineRegisterInfo {
/// freezeReservedRegs - Called by the register allocator to freeze the set
/// of reserved registers before allocation begins.
- void freezeReservedRegs(const MachineFunction&);
+ void freezeReservedRegs();
/// reserveReg -- Mark a register as reserved so checks like isAllocatable
/// will not suggest using it. This should not be used during the middle
diff --git a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
index 54f55623131b35..e09318a486955b 100644
--- a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
@@ -574,7 +574,7 @@ MIRParserImpl::initializeMachineFunction(const yaml::MachineFunction &YamlMF,
// FIXME: This is a temporary workaround until the reserved registers can be
// serialized.
MachineRegisterInfo &MRI = MF.getRegInfo();
- MRI.freezeReservedRegs(MF);
+ MRI.freezeReservedRegs();
computeFunctionProperties(MF);
diff --git a/llvm/lib/CodeGen/MachineOutliner.cpp b/llvm/lib/CodeGen/MachineOutliner.cpp
index b8d3b2e30e6e6a..dc2f5ef15206e8 100644
--- a/llvm/lib/CodeGen/MachineOutliner.cpp
+++ b/llvm/lib/CodeGen/MachineOutliner.cpp
@@ -759,7 +759,7 @@ MachineFunction *MachineOutliner::createOutlinedFunction(
MF.getProperties().set(MachineFunctionProperties::Property::NoPHIs);
MF.getProperties().set(MachineFunctionProperties::Property::NoVRegs);
MF.getProperties().set(MachineFunctionProperties::Property::TracksLiveness);
- MF.getRegInfo().freezeReservedRegs(MF);
+ MF.getRegInfo().freezeReservedRegs();
// Compute live-in set for outlined fn
const MachineRegisterInfo &MRI = MF.getRegInfo();
diff --git a/llvm/lib/CodeGen/MachineRegisterInfo.cpp b/llvm/lib/CodeGen/MachineRegisterInfo.cpp
index e88487fcc9f9e7..55d7c8370e9c46 100644
--- a/llvm/lib/CodeGen/MachineRegisterInfo.cpp
+++ b/llvm/lib/CodeGen/MachineRegisterInfo.cpp
@@ -517,8 +517,8 @@ LLVM_DUMP_METHOD void MachineRegisterInfo::dumpUses(Register Reg) const {
}
#endif
-void MachineRegisterInfo::freezeReservedRegs(const MachineFunction &MF) {
- ReservedRegs = getTargetRegisterInfo()->getReservedRegs(MF);
+void MachineRegisterInfo::freezeReservedRegs() {
+ ReservedRegs = getTargetRegisterInfo()->getReservedRegs(*MF);
assert(ReservedRegs.size() == getTargetRegisterInfo()->getNumRegs() &&
"Invalid ReservedRegs vector from target");
}
@@ -660,17 +660,14 @@ bool MachineRegisterInfo::isReservedRegUnit(unsigned Unit) const {
return false;
}
-bool MachineRegisterInfo::isArgumentRegister(const MachineFunction &MF,
- MCRegister Reg) const {
- return getTargetRegisterInfo()->isArgumentRegister(MF, Reg);
+bool MachineRegisterInfo::isArgumentRegister(MCRegister Reg) const {
+ return getTargetRegisterInfo()->isArgumentRegister(*MF, Reg);
}
-bool MachineRegisterInfo::isFixedRegister(const MachineFunction &MF,
- MCRegister Reg) const {
- return getTargetRegisterInfo()->isFixedRegister(MF, Reg);
+bool MachineRegisterInfo::isFixedRegister(MCRegister Reg) const {
+ return getTargetRegisterInfo()->isFixedRegister(*MF, Reg);
}
-bool MachineRegisterInfo::isGeneralPurposeRegister(const MachineFunction &MF,
- MCRegister Reg) const {
- return getTargetRegisterInfo()->isGeneralPurposeRegister(MF, Reg);
+bool MachineRegisterInfo::isGeneralPurposeRegister(MCRegister Reg) const {
+ return getTargetRegisterInfo()->isGeneralPurposeRegister(*MF, Reg);
}
diff --git a/llvm/lib/CodeGen/RegAllocBase.cpp b/llvm/lib/CodeGen/RegAllocBase.cpp
index 900f0e9079d698..d0dec372f68961 100644
--- a/llvm/lib/CodeGen/RegAllocBase.cpp
+++ b/llvm/lib/CodeGen/RegAllocBase.cpp
@@ -61,7 +61,7 @@ void RegAllocBase::init(VirtRegMap &vrm, LiveIntervals &lis,
VRM = &vrm;
LIS = &lis;
Matrix = &mat;
- MRI->freezeReservedRegs(vrm.getMachineFunction());
+ MRI->freezeReservedRegs();
RegClassInfo.runOnMachineFunction(vrm.getMachineFunction());
}
diff --git a/llvm/lib/CodeGen/RegAllocFast.cpp b/llvm/lib/CodeGen/RegAllocFast.cpp
index e81d4793013682..6740e1f0edb4f4 100644
--- a/llvm/lib/CodeGen/RegAllocFast.cpp
+++ b/llvm/lib/CodeGen/RegAllocFast.cpp
@@ -1740,7 +1740,7 @@ bool RegAllocFast::runOnMachineFunction(MachineFunction &MF) {
TRI = STI.getRegisterInfo();
TII = STI.getInstrInfo();
MFI = &MF.getFrameInfo();
- MRI->freezeReservedRegs(MF);
+ MRI->freezeReservedRegs();
RegClassInfo.runOnMachineFunction(MF);
unsigned NumRegUnits = TRI->getNumRegUnits();
UsedInInstr.clear();
diff --git a/llvm/lib/CodeGen/RegAllocPBQP.cpp b/llvm/lib/CodeGen/RegAllocPBQP.cpp
index b8ee5dc0f8494b..aea92788057971 100644
--- a/llvm/lib/CodeGen/RegAllocPBQP.cpp
+++ b/llvm/lib/CodeGen/RegAllocPBQP.cpp
@@ -809,7 +809,7 @@ bool RegAllocPBQP::runOnMachineFunction(MachineFunction &MF) {
std::unique_ptr<Spiller> VRegSpiller(
createInlineSpiller(*this, MF, VRM, DefaultVRAI));
- MF.getRegInfo().freezeReservedRegs(MF);
+ MF.getRegInfo().freezeReservedRegs();
LLVM_DEBUG(dbgs() << "PBQP Register Allocating for " << MF.getName() << "\n");
diff --git a/llvm/lib/CodeGen/TargetLoweringBase.cpp b/llvm/lib/CodeGen/TargetLoweringBase.cpp
index a2aeb66835b29e..8ac55ee6a5d0c1 100644
--- a/llvm/lib/CodeGen/TargetLoweringBase.cpp
+++ b/llvm/lib/CodeGen/TargetLoweringBase.cpp
@@ -2336,7 +2336,7 @@ bool TargetLoweringBase::isLoadBitCastBeneficial(
}
void TargetLoweringBase::finalizeLowering(MachineFunction &MF) const {
- MF.getRegInfo().freezeReservedRegs(MF);
+ MF.getRegInfo().freezeReservedRegs();
}
MachineMemOperand::Flags TargetLoweringBase::getLoadMemOperandFlags(
diff --git a/llvm/lib/Target/AArch64/AArch64LowerHomogeneousPrologEpilog.cpp b/llvm/lib/Target/AArch64/AArch64LowerHomogeneousPrologEpilog.cpp
index 4afc678abaca63..d21aa59659a25d 100644
--- a/llvm/lib/Target/AArch64/AArch64LowerHomogeneousPrologEpilog.cpp
+++ b/llvm/lib/Target/AArch64/AArch64LowerHomogeneousPrologEpilog.cpp
@@ -183,7 +183,7 @@ static MachineFunction &createFrameHelperMachineFunction(Module *M,
MF.getProperties().reset(MachineFunctionProperties::Property::TracksLiveness);
MF.getProperties().reset(MachineFunctionProperties::Property::IsSSA);
MF.getProperties().set(MachineFunctionProperties::Property::NoVRegs);
- MF.getRegInfo().freezeReservedRegs(MF);
+ MF.getRegInfo().freezeReservedRegs();
// Create entry block.
BasicBlock *EntryBB = BasicBlock::Create(C, "entry", F);
diff --git a/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp b/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp
index 0c57110b4eb15d..398f870a9f5311 100644
--- a/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp
+++ b/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp
@@ -156,7 +156,7 @@ void SIPreAllocateWWMRegs::rewriteRegs(MachineFunction &MF) {
RegsToRewrite.clear();
// Update the set of reserved registers to include WWM ones.
- MRI->freezeReservedRegs(MF);
+ MRI->freezeReservedRegs();
}
#ifndef NDEBUG
diff --git a/llvm/tools/llvm-exegesis/lib/Assembler.cpp b/llvm/tools/llvm-exegesis/lib/Assembler.cpp
index 3aad9135978968..92ab3a96d91e6b 100644
--- a/llvm/tools/llvm-exegesis/lib/Assembler.cpp
+++ b/llvm/tools/llvm-exegesis/lib/Assembler.cpp
@@ -305,7 +305,7 @@ Error assembleToStream(const ExegesisTarget &ET,
// prologue/epilogue pass needs the reserved registers to be frozen, this
// is usually done by the SelectionDAGISel pass.
- MF.getRegInfo().freezeReservedRegs(MF);
+ MF.getRegInfo().freezeReservedRegs();
// We create the pass manager, run the passes to populate AsmBuffer.
MCContext &MCContext = MMIWP->getMMI().getContext();
diff --git a/llvm/tools/llvm-reduce/ReducerWorkItem.cpp b/llvm/tools/llvm-reduce/ReducerWorkItem.cpp
index 353216766717e3..78e6f72d7032d5 100644
--- a/llvm/tools/llvm-reduce/ReducerWorkItem.cpp
+++ b/llvm/tools/llvm-reduce/ReducerWorkItem.cpp
@@ -414,7 +414,7 @@ static std::unique_ptr<MachineFunction> cloneMF(MachineFunction *SrcMF,
if (!DstMF->cloneInfoFrom(*SrcMF, Src2DstMBB))
report_fatal_error("target does not implement MachineFunctionInfo cloning");
- DstMRI->freezeReservedRegs(*DstMF);
+ DstMRI->freezeReservedRegs();
DstMF->verify(nullptr, "", /*AbortOnError=*/true);
return DstMF;
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